numbers of lanes QSYS Cyclone V hard IP for PCI Express

PCIe is bidirectional and full duplex. Each lane consists of two separate diff pairs - one Rx and one Tx. What exactly are you asking? The JPEG you attached is too small to see, so can't comment on your Qsys setup.

If you're asking why only one Rx and one Tx interface is shown when each consists of a diff pair, think logical vs. physical here. Qsys is not going to show you the + and - wires of each pair, but they are there.

thanks for your response!!!

Well, I'm try to simulate a PCIe comunication but when I see the "pines" of lanes I noticed that I don't have ones "pines" (I've selected a x1 lane and I just have a Rx and Tx).

but I've got some questions:

I found that simulation doesnt need diff pairs...Is it correct?

Now, when I must assigment I/O of Interface PCIe to hardware , Do I need add another interface like "Transceivers Reconfiguration Controller"??

"pines" = Spanish for pins?

I think you're correct that simulation does not need diff pairs (I have not simulated PCIe).

No need to instantiate a reconfiguration controller. The hard IP includes everything needed for the transceivers.

But, How hard IP assigment the I/O (Qsys make me a entity of interface) to pins???

When I see the interface I only see one Tx and Rx......the pin planer I see two Rx and Tx (diff pairs).

How can I assign one Tx and Rx (I/O of entity make bye Qsys) to two Tx and Rx of pin Planer???

--- Quote Start ---

But, How hard IP assigment the I/O (Qsys make me a entity of interface) to pins???

When I see the interface I only see one Tx and Rx......the pin planer I see two Rx and Tx (diff pairs).

How can I assign one Tx and Rx (I/O of entity make bye Qsys) to two Tx and Rx of pin Planer???

--- Quote End ---

You only need to assign the pins in your top-level port list to the + pins of the diff pairs. The Pin Planner automatically creates and assigns the - pins (they show up as your port names with (n) appended).

Sometimes I wish Altera just stuck with the physical representation of diff pairs instead of hiding the details. It does get confusing at times.

Ok, thank for your response.

rsefton, do you have some file where I can see how to assign the I/O of entity to pins???

--- Quote Start ---

Ok, thank for your response.

rsefton, do you have some file where I can see how to assign the I/O of entity to pins???

--- Quote End ---

There are very specific requirements for the placement of PCIe channels when using the PCIe hard IP. See this document:

https://www.altera.com/en_us/pdfs/literature/ug/ug_c5_pcie_avmm.pdf

Start reading on page 4-26. If this doesn't give you enough information then download a PCIe reference design and look at the pin assignments in the .qsf file. Here's an example for Cyclone V:

http://www.altera.com/support/refdesigns/ip/interface/pcie_cvgt_avst_on_chip_mem_150.zip

Good luck.

Please, I've got the last questions.

You did tell me that I only need to assign the I/O of entity to + pins (in pin planner I can see the + and - transceivers......please, see the image that I've attached....the red square is + pin).

My quiestion is:

When I complete to assign all my I/O to FPGA's pins.... Do I have to start compilation and I only wait quartus finish the compilation?? and after of compilation...

Will Quartus have finished assigning the I/O of entity to + and - pins??