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Ok, thank for your response.
rsefton, do you have some file where I can see how to assign the I/O of entity to pins???
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There are very specific requirements for the placement of PCIe channels when using the PCIe hard IP. See this document:
https://www.altera.com/en_us/pdfs/literature/ug/ug_c5_pcie_avmm.pdf Start reading on page 4-26. If this doesn't give you enough information then download a PCIe reference design and look at the pin assignments in the .qsf file. Here's an example for Cyclone V:
http://www.altera.com/support/refdesigns/ip/interface/pcie_cvgt_avst_on_chip_mem_150.zip Good luck.
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