Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributornumbers of lanes QSYS Cyclone V hard IP for PCI Express
Hi guys I need your helping please. I'm using Qsys and I've selected a PCIe interface. When I customized amount lanes I've selected x1 lanes, but when I watched the interface I've noticed tha...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Ok, thank for your response. rsefton, do you have some file where I can see how to assign the I/O of entity to pins??? --- Quote End --- There are very specific requirements for the placement of PCIe channels when using the PCIe hard IP. See this document: https://www.altera.com/en_us/pdfs/literature/ug/ug_c5_pcie_avmm.pdf Start reading on page 4-26. If this doesn't give you enough information then download a PCIe reference design and look at the pin assignments in the .qsf file. Here's an example for Cyclone V: http://www.altera.com/support/refdesigns/ip/interface/pcie_cvgt_avst_on_chip_mem_150.zip Good luck.
