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Altera_Forum's avatar
Altera_Forum
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9 years ago

numbers of lanes QSYS Cyclone V hard IP for PCI Express

Hi guys I need your helping please. I'm using Qsys and I've selected a PCIe interface. When I customized amount lanes I've selected x1 lanes, but when I watched the interface I've noticed tha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Please, I've got the last questions.

You did tell me that I only need to assign the I/O of entity to + pins (in pin planner I can see the + and - transceivers......please, see the image that I've attached....the red square is + pin).

My quiestion is:

When I complete to assign all my I/O to FPGA's pins.... Do I have to start compilation and I only wait quartus finish the compilation?? and after of compilation...

Will Quartus have finished assigning the I/O of entity to + and - pins??