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Hi Fakhrul,
Thanks for the review.
We have checked the above list and it is fulfilled.
Actually we have noticed that after failure there is success and so on : pass-fail-pass-fail-pass-fail...
The power is stable during the test. A failing condition occurs before ALERT goes low. It is always after a specific number of AVST Clocks; the process fails after 4130 AVST_CLK cycles.
nConfig/nStatus start ok .
I haven't read STATUS BYTE after nStatus went low because PMBus activity has not started yet. Please suggest if this can lead to something.
Thanks,
Itzik
- FakhrulA_altera24 days ago
Regular Contributor
Hi Itzik,
Thanks for the details. Since the failure is repeatable after a fixed 4130 AVST_CLK cycles and happens before ALERT, this points to the AVST configuration stream rather than PMBus.
Could please try the following?
Raise AVST_CLK and verify VALID/READY handling
Use a faster AVST clock (target ≥1 MHz). Keep AVST_VALID high while streaming; when AVST_READY goes low, send idle clocks with VALID=0. Capture AVST_CLK, AVST_VALID, AVST_READY, and data around the 4130‑cycle point. This fixed similar stall-at-a-fixed-count cases. https://community.altera.com/discussions/boards-and-dev-kits/agilex-3-avst-programming-fails/122255
Read SDM status immediately after nSTATUS drops
Use the AN‑936 method or Configuration Debugger to read SDM major/minor codes right after the failure. It will tell whether the drop was due to AVST stream, PMBus, or another SDM check, guiding the next fix. KDB: [community.altera.com]
Regards,
Fakhrul
- FakhrulA_altera18 days ago
Regular Contributor
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