Novice ask for advice! I use the Deterministic Latency mode of serdes

Firstly,Thanks for your attention,my english is very poor, I wish you can understand

me.

Now,I use Cyclone IV GX EP4CGX75CF23, use the Deterministic Latency mode of serdes. I found that when the "rx_patterndetect" signal asserted,the "rx_dataout" value was not 0xBC(K28.5),neither in the left nor the right, I can't see the 0xBC

I know sometimes the "rx_patterndetect" signal maybe not appear right with the 0xBC,so I tried it in another way.

In the transmit port, I send the words alignment "0x5A5A5A5A5A5ABC" as the frame head(of course,I only assert the "tx_ctrlenable" signal when I send the 0xBC); in the receive port, I would not check the "rx_patterndetect" signal and "rx_dataout" value equal to 0xBC, I set a 7*8bits=56bits buffer,like a FIFO. When I find that if the buffer equal to 0x5A5A5A5A5A5ABC, I treat it as the frame head(the percent of misjudge is only 1/(2^56) ). For test,my code is this: once I receive the words alignment ,I assert a flag until external reset or have not receive "rx_patterndetect" signal for a long time(the determine value you can set yourself,my number is 40 frames). When it works,in the receive port, I slip 1 time each 2 frame,if I can't detect the "rx_patterndetect" signal asserted. So in theory

, in every 2*8 frame time, I should receive a 0xBC,and 40 frames time is enough for me check 2 times.

But, by the signaltab ii, I found that even the "rx_patterndetect" signal and "rx_dataout" are all right in some moment, the flags are all or part been not asserted.

Would someone can help me? Thank U very much!