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Altera_Forum's avatar
Altera_Forum
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16 years ago

Non-tristate cfi flash component in sopc

Hi all,

In my system, user logic and sopc system both access cfi flash device(Numonyx 128P30) in TDM mode(time division multiplex). Additional, the flash is AP configuration device for EP3C25.

In top level design, I will connect sopc's tristate flash dq signals and user logic's signals to the related signals of cfi flash device.

We all know Altera's FPGA don't support internal tristate signals. So the sopc system with default cfi flash component can't fit into my design.

I think one way to resolve this problem is design new cfi flash component in which the data bus is separate to input_data and output_data, finally tristate these signals in top level deisgn(out of sopc system).

But I am not familiar with new sopc component build. Can anyone give me some advice or similar design template?

Thanks a lot!

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You can multiplex/demultiplex the cfi bus outside the SOPC system, using the read/write signal to detect the direction of the connexion you make.

    A nicer solution would be to have your user logic inside the SOPC system, with an Avalon master interface to access the flash. That way, arbitration between your logic and the rest of the SOPC system would be handled automatically.

    Of course in that case you need to learn how to make SOPC components. You can start by reading that page (http://www.altera.com/support/software/system/sopc/sof-sopc-development-flow.html), and the linked documentation.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi Daixiwen,

    Thanks for your reply.

    According to your first idea, I have read a typical sopc generated "xxx.v" file, the flash input_data and output_data signals is easy to bring outside sopc. The disadvantage of this way is each time after generate new sopc system, user should manually edit the "xxx.v" file. I'll try it asap.

    Thank you again!
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi Daixiwen,

    Thanks for your reply.

    According to your first idea, I have read a typical sopc generated "xxx.v" file, the flash input_data and output_data signals is easy to bring outside sopc. The disadvantage of this way is each time after generate new sopc system, user should manually edit the "xxx.v" file. I'll try it asap.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I don't understand... the flash signals should be already exported by the SOPC component, you shouldn't have to edit the verilog file to do that... Could you show us your SOPC configuration?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi Daixiwen,

    I have complete the design, and verify ok. Both user logic and nios can boot from cfi flash now.

    But there is a strange problem in this design: nios/e can't boot, but nios/s is ok. It waste me almost 1 day to find this problem. Maybe my hardware has something not very fit for nios's requirement.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    What do you mean by "can't boot"? Does it get stuck somewhere? Did you try to run a debugger to see what happens?

    Can you show us your SOPC configuration?