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Altera_Forum
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11 years ago

Node instance "tcm_address_w_check" instantiates undefined entity

Hello. I am using Quartus 13.1 and Qsys. I can build my project using verilog, qsys and NIOS previously. But I added the clock component at pll in qsys. I had error at build of quartus (usin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thank you for responding.

I used Avalon_ATTPLL.

I used Edit. At Output/Clock tab, I set c3 and c4 clock data.

And I build the connection to dualport RAM at system components in qsys.

Best Regards,