no output clock when using ip toolbench-generated ddr2 controller

I am using the self-contained ip core within quartus ii 8.0 to generate ddr2 controller. after full compilation, i simulate using the quartus8.0-generated .vo and .sdo files(and testbench file) within modelsim se 6.5, but clk_to_sdram and clk_to_sdram_n which should output to ddr2 sdram are tied to 0 and 1 without changing. when using ddr controller, however, the clk_to_sdram and clk_to_sdram_n are ok.

The testing environment is as following:

FPGA:EP2C50F672C6

DDR2 Controller:ddr2 sdram controller v8.0 within Quartus ii 8.0 Megawizard

Files:use quartus-generated project files and testbench files; ddr2 model file is downloaded from micron website.

can anyone help me?

Thanks ahead.