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Altera_Forum
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8 years ago

No logic elements although I have an output

Hello Please guide me why I don't see any logic element for the current code : LIBRARY ieee; USE ieee.std_logic_1164.all; Use ieee.numeric_std.all; USE work.my_data_types.all; -- to def...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

You will benefit from Drawing the circuit you expect before writing any code. When writing VHDL you need to understand the circuit you're creating - it is VHSIC Hardware description language. So you need to know what hardware you are describing.