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Altera_Forum
Honored Contributor
Honored ContributorNo logic elements although I have an output
Hello Please guide me why I don't see any logic element for the current code : LIBRARY ieee; USE ieee.std_logic_1164.all; Use ieee.numeric_std.all; USE work.my_data_types.all; -- to def...
Altera_ForumHonored Contributor
Honored ContributorYou cant "get more time"
Remmeber that all processes run simultaneously. All assignments happen in parrellel I suggest reviewing your VHDL training materials. This is NOT like software programming.
