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Altera_Forum's avatar
Altera_Forum
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15 years ago

NIOSII Program doesn't execute

Hello everybody,

I'm new with Altera and the NIOSII an have got a Problem with the execution of a NIOSII Program. I'm using the Altera Cyclone III Starter Board ( NEEK ) with an Altera CycloneIII EP3C25 FPGA.

I've built a NIOSII System including the following components:

- onchip_memory

- cpu (NIOSII/s)

- tri_state_bridge

- SRAM_Controller (cypress CY7C1380C SSRAM)

- interval timer

- PIO for leds and buttons

- altpll for SRAM-clocl

- system id

The system was synthesized with QuartusII 10.0 sp1 web edition, without errors.

Now i have written a simple C-Program with NIOSII eds and tried to execute it, but it doesent run. There are no errors while building or running the Project. I tried to debug the project but there is no debug-cursor on the code and there is no Disassemby, Variables or Registers.

It seems like the processor starts at the wrong address. Is this possible??

How can i figure out whether the processor runs or not??

Can anybody please tell me how i can go on to solve the problem?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Is the JTAG debug module enabled in the Nios CPU? Are both the data and instruction masters connected to the JTAG debug port in SOPC builder?

    You should add a JTAG UART to your project too, and then you should be able to use a console with standard input/output.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hello Daixiwen, thanks for yout reply!

    Yes, the JTAG debug module is enabled (Level 1), and both data and instruction masters are connected.

    I've also got a JTAG-UART (sorry, i've forgot it in the upper list) and tried to

    write something via printf(), but there was no output.

    My program only doesn't work when the SSRAM controller is incuded in the system. I think there is a problem with this contoller or my PLL component.

    There are some warnings at the compilation of the design, so now i try to correct the warnings!

    Thanks for the tips!
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Could you compile a memory test software (from the template list), and be sure to run it from the on-chip memory (be sure in the BSP configuration that all the sections go to the on-chip memory).

    That way you can test the SSRAM interface.