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Altera_Forum's avatar
Altera_Forum
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16 years ago

NIOS II top level in Quartus II

When compiling the source files generated by SoPC Builder in Quartus II, is it necessary to make a top-level entity? SoPC Builder generates a file called nios_system_name.v which I set as the top level entity in Quartus and the compilation works. Note, that I am not integrating the nios system with any other design. I'm just compiling the system and putting it on an FPGA. Do I still need to make this top-level entity?

Thanks.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I prefer using top level logic, but so long as you connect your SOPC Builder top-level to pins, you should be okay.

    - slacker
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I didnt do any sort of connection with pins (if you're referring to bdf file). All I did was add all the verilog files from SoPC builder and pin assignment then compiled. Could you please elaborate on your method.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    "pin assignment" would be what I was referring to...when I stated "connect to pins". FPGA's connection to the off-chip world would be another analogy. :-)

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    I didnt do any sort of connection with pins (if you're referring to bdf file). All I did was add all the verilog files from SoPC builder and pin assignment then compiled. Could you please elaborate on your method.

    --- Quote End ---

    Hi,

    when you look into your verilog file you will find inputs and outputs. I would expect at least a clock and a reset input. When you will run your design on a certain board you have to make proper pin assignments.

    Kind regards

    GPK