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Altera_Forum
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15 years ago

Nios II software

Hi, I'm new to developing Altera fpga hardware & software designs. Does anyone know where can I find some literature regarding the direct use of hardware design by nios II software?

Example>

I have designed a fpga that contains several 9x9-bit multipliers. Can I somehow set or reset values of data1 and data2 operands of the 3rd multiplier directly from the C or C++ source code? How can I manipulate these inputs and outputs if it is possible?

Many thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Read the part about conduits in the Avalon documentation. You can map a conduit in memory and write and read from it on the Nios side. On the other side, you will have to interpret the signals -- this is very clearly specified in the Avalon documentation. You can start with this module definition... 

    
module conduit    (// Slave interface
                   input csi_clock_clk,
                   input csi_clock_reset_n,
                 
                   input     avs_s1_address,
                   input          avs_s1_read,
                   input          avs_s1_write,
                   input    avs_s1_writedata,
                   output   avs_s1_readdata,
                   output         avs_s1_waitrequest,
                 
                   // Conduit
                   output         coe_user_clk,
                   output         coe_user_reset_n,
                   output    coe_user_address,
                   output         coe_user_read,
                   output         coe_user_write,
                   output   coe_user_writedata,
                   input    coe_user_readdata,
                   input          coe_user_waitrequest);

    Please note that the csi, avs, and coe prefixes are needed there so that SOPC can easily interpret what your signals mean. You will need this snippet after you try to create a custom component in SOPC...
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thank you very much ironmoose. I read the Avalon interface specifications. However I have another, suppose much simpler question for you, regarding parallel computing with dsp-multipliers (organizing them as multipliers) and manipulating them by the compiled c-code, and I do not understand completely and how do things work in a configured fpga chip.

    I want to do somehow this:

    a*b = c, d*e = f, g*h = i, j*k = l, m*n = o;

    in my c,c++ code in a single clock cycle on a fpga by 5 dsp-multipliers configured on it.

    1]How do I execute all 5 multiplication operations in a single clock cycle? How do I make it parallel in my code?

    2]Or is there a special library that includes concurrent code writing in c,c++?

    Does every instruction (of multiplication) go through fetch and load cycle and is done by NiosII processor, so that every single multiplication needs to have the processor involved? or the circuitry configured with those five dsp-multipliers does that without processor? Is the circuitry "parallel" itself?

    3] Are there any other methods for doing this, perhaps configuring differently the hardware, or can be done by software?

    Thank you in advance, hope I made myself a bit more clear than the last time.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I think you'll need to create your own SOPC component to do that, using the Avalon Interfaces. I don't think that using C/C++ code and the C2H compiler will automatically create 5 parallel multipliers.

    You may have a problem fetching the data though, because loading 10 integers per clock cycle will require some bandwidth (or an on-chip RAM with a very large data bus)
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If you were hoping to see the results of the DSPs in your code every cycle, you won't. There are all kinds of latencies depending on which NIOS core you use and whether you have interrupts or not. Your best bet would be to implement a larger part of your algorithm in HDL and hopefully it would produce results (and consume input) at a slower rate; slow enough that the software latencies are not a factor. In this case, you would use a DMA-like scheme... i.e. 1- load a bunch of data into memory (preferably FPGA RAM as suggested above), 2- FPGA does all the calculations... 3- DMA back to CPU RAM and use the results.