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Honored Contributor
Honored ContributorNIOS II Simulation Error
Hi again.
I have a simple system with Nios II e, SDRAM, On-Chip memory, JTAG-UART and Sys-ID Peripheral. I created "Hello World" in the NIos II Eclipse IDE and it runs, I get "Hello from Nios II!" in the Nios II Console. When I start the simulation with Modelsim, I become errors in two locations in the testbench code. First: process (clk, reset_n)
VARIABLE write_line6 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((W_valid AND R_wr_dst_reg)) = '1' then
if is_x(R_dst_regnum) then
write(write_line6, now);
write(write_line6, string'(": "));
write(write_line6, string'("ERROR: cpu_0_test_bench/R_dst_regnum is 'x'"));
write(output, write_line6.all & CR);
deallocate (write_line6);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process; process (clk, reset_n)
VARIABLE write_line13 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((i_read AND NOT i_waitrequest)) = '1' then
if is_x(i_readdata) then
write(write_line13, now);
write(write_line13, string'(": "));
write(write_line13, string'("ERROR: cpu_0_test_bench/i_readdata is 'x'"));
write(output, write_line13.all & CR);
deallocate (write_line13);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
