NIOS II Simulation Error

Ok, thank you, Daixiwen, got it now. Seems like there is something wrong with SDRAM testbench model. If I link all data (.bss, .text, .heap.....) to the on-chip memory, simulation runs.

What do i need to do to simulate SDRAM? I work with SOPC-Builder and VHDL. Tutorials I found were in Qsys and Verilog, so it was not realy helpfull.

So I turned on "Include a functional memory model in the system testbench" in the SDRAM properties in SOPC-Builder and regenerated the system. Also I turned on "enable_sim_optimize" in BSP-Editor options (NIOS II SBT for Eclipse).

In Modelsim, after 's' -> 'w' -> 'run 5ms' I get

# ************************************************************

# This testbench includes an SOPC Builder Generated Altera model:

# 'sdram_0_test_component.vhd', to simulate accesses to SDRAM.

# Initial contents are loaded from the file: 'sdram_0.dat'.

# ************************************************************

.....seems to be right I think.

But in the waveform the signals az_addr and az_data are X all the time. za_data is Z after reset, 0 during the reset.

Do I have to wire up something? I'm realy new with all this stuff and to work through the generated code, I will need realy long time. Would be nice, if someone could help or give me a hint.

Thank you!