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Altera_Forum
Honored Contributor
Honored ContributorNios DDR3 Test Example Project TimeQuest Negative Setup Slack
Hello everyone, I've been trying to understand the workings of the timing analyser recently. I need to implement an SDRAM Controller with Uniphy in my design. So I opened up an example pro...
Altera_ForumHonored Contributor
Honored ContributorOh I'm sorry about the screenshot
Please try this link https://imgur.com/a/yr9ldwm (https://imgur.com/a/yr9ldwm) The sdc file from the previous post was the generated sdc file. I just added the clock groups to see if that solves the failure. I added the source project folder to my attachments. This is in its original form. I would appreciate any help.
