DDR3_Qsys |

2013.04.18.15:28:34 | Datasheet

Overview

clk_50 | DDR3_Qsys

Processor
nios2_qsys Nios II 13.0
All Components
mem_if_ddr3_emif_fpga altera_mem_if_ddr3_emif 13.0
nios2_qsys altera_nios2_qsys 13.0
onchip_memory2 altera_avalon_onchip_memory2 13.0.1
jtag_uart altera_avalon_jtag_uart 13.0.1
timer altera_avalon_timer 13.0.1
sysid_qsys altera_avalon_sysid_qsys 13.0
key altera_avalon_pio 13.0.1
ddr3_status altera_avalon_pio 13.0.1
Memory Map

| nios2_qsys
data_master | instruction_master
mem_if_ddr3_emif_fpga |  |
avl | 0x00000000 |
nios2_qsys |  |
jtag_debug_module | 0x40040800 | 0x40040800
onchip_memory2 |  |
s1 | 0x40020000 | 0x40020000
jtag_uart |  |
avalon_jtag_slave | 0x40041048 |
timer |  |
s1 | 0x40041000 |
sysid_qsys |  |
control_slave | 0x40041040 |
key |  |
s1 | 0x40041030 |
ddr3_status |  |
s1 | 0x40041020 |

## clk_50

clock_source v13.0

## Parameters
clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## mem_if_ddr3_emif_fpga

altera_mem_if_ddr3_emif v13.0

clk_50 | clk_reset | mem_if_ddr3_emif_fpga
soft_reset
clk
pll_ref_clk
clk_reset
global_reset
nios2_qsys | data_master
avl

## Parameters
AC_ROM_MR0 | 0001000100001
AC_ROM_MR0_MIRR | 0001001000001
AC_ROM_MR0_CALIB |
AC_ROM_MR0_DLL_RESET | 0001100100000
AC_ROM_MR0_DLL_RESET_MIRR | 0001011000000
AC_ROM_MR1 | 0000001000110
AC_ROM_MR1_MIRR | 0000000100110
AC_ROM_MR1_CALIB |
AC_ROM_MR1_OCD_ENABLE |
AC_ROM_MR2 | 0001000000000
AC_ROM_MR2_MIRR | 0001000000000
AC_ROM_MR3 | 0000000000000
AC_ROM_MR3_MIRR | 0000000000000
MR0_BL | 1
MR0_BT | 0
MR0_CAS_LATENCY | 2
MR0_DLL | 1
MR0_WR | 1
MR0_PD | 0
MR1_DLL | 0
MR1_ODS | 1
MR1_RTT | 3
MR1_AL | 0
MR1_WL | 0
MR1_TDQS | 0
MR1_QOFF | 0
MR1_DQS | 0
MR1_RDQS | 0
MR2_CWL | 0
MR2_ASR | 0
MR2_SRT | 0
MR2_SRF | 0
MR2_RTT_WR | 1
MR3_MPR_RF | 0
MR3_MPR | 0
MR3_MPR_AA | 0
MEM_IF_READ_DQS_WIDTH | 4
MEM_IF_WRITE_DQS_WIDTH | 4
MEM_IF_ADDR_WIDTH | 15
MEM_IF_ADDR_WIDTH_MIN | 13
MEM_IF_ROW_ADDR_WIDTH | 15
MEM_IF_COL_ADDR_WIDTH | 10
MEM_IF_DM_WIDTH | 4
MEM_IF_CS_PER_RANK | 1
MEM_IF_NUMBER_OF_RANKS | 1
MEM_IF_CS_PER_DIMM | 1
MEM_IF_CONTROL_WIDTH | 1
MEM_BURST_LENGTH | 8
MEM_LEVELING | false
MEM_IF_DQS_WIDTH | 4
MEM_IF_CS_WIDTH | 1
MEM_IF_CHIP_BITS | 1
MEM_IF_BANKADDR_WIDTH | 3
MEM_IF_DQ_WIDTH | 32
MEM_IF_CK_WIDTH | 1
MEM_IF_CLK_EN_WIDTH | 1
MEM_IF_CLK_PAIR_COUNT | 1
DEVICE_WIDTH | 1
MEM_CLK_MAX_NS | 2.5
MEM_CLK_MAX_PS | 2500.0
MEM_TRC | 16
MEM_TRAS | 12
MEM_TRCD | 5
MEM_TRP | 5
MEM_TREFI | 2341
MEM_TRFC | 91
CFG_TCCD | 1
MEM_TWR | 5
MEM_TFAW | 16
MEM_TRRD | 4
MEM_TRTP | 4
MEM_DQS_TO_CLK_CAPTURE_DELAY | 450
MEM_CLK_TO_DQS_CAPTURE_DELAY | 100000
MEM_IF_ODT_WIDTH | 1
MEM_WTCL_INT | 5
FLY_BY | true
RDIMM | false
LRDIMM | false
RDIMM_INT | 0
LRDIMM_INT | 0
MEM_IF_RD_TO_WR_TURNAROUND_OCT | 2
MEM_IF_WR_TO_RD_TURNAROUND_OCT | 3
CTL_RD_TO_PCH_EXTRA_CLK | 0
CTL_RD_TO_RD_EXTRA_CLK | 0
CTL_WR_TO_WR_EXTRA_CLK | 0
CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK | 1
CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK | 1
MEM_TYPE | DDR3
MEM_MIRROR_ADDRESSING_DEC | 0
MEM_ATCL_INT | 0
MEM_REGDIMM_ENABLED | false
MEM_LRDIMM_ENABLED | false
MEM_VENDOR | JEDEC
MEM_FORMAT | DISCRETE
AC_PARITY | false
RDIMM_CONFIG | 0
LRDIMM_EXTENDED_CONFIG | 0x000000000000000000
DISCRETE_FLY_BY | true
DEVICE_DEPTH | 1
MEM_MIRROR_ADDRESSING | 0
MEM_CLK_FREQ_MAX | 400.0
MEM_ROW_ADDR_WIDTH | 15
MEM_COL_ADDR_WIDTH | 10
MEM_DQ_WIDTH | 32
MEM_DQ_PER_DQS | 8
MEM_BANKADDR_WIDTH | 3
MEM_IF_DM_PINS_EN | true
MEM_IF_DQSN_EN | true
MEM_NUMBER_OF_DIMMS | 1
MEM_NUMBER_OF_RANKS_PER_DIMM | 1
MEM_NUMBER_OF_RANKS_PER_DEVICE | 1
MEM_RANK_MULTIPLICATION_FACTOR | 1
MEM_CK_WIDTH | 1
MEM_CS_WIDTH | 1
MEM_CLK_EN_WIDTH | 1
ALTMEMPHY_COMPATIBLE_MODE | false
NEXTGEN | true
MEM_IF_BOARD_BASE_DELAY | 10
MEM_IF_SIM_VALID_WINDOW | 0
MEM_GUARANTEED_WRITE_INIT | false
MEM_VERBOSE | true
PINGPONGPHY_EN | false
REFRESH_BURST_VALIDATION | false
MEM_BL | OTF
MEM_BT | Sequential
MEM_ASR | Manual
MEM_SRT | Normal
MEM_PD | DLL off
MEM_DRV_STR | RZQ/7
MEM_DLL_EN | true
MEM_RTT_NOM | RZQ/6
MEM_RTT_WR | RZQ/4
MEM_WTCL | 5
MEM_ATCL | Disabled
MEM_TCL | 6
MEM_AUTO_LEVELING_MODE | true
MEM_USER_LEVELING_MODE | Leveling
MEM_INIT_EN | false
MEM_INIT_FILE |
DAT_DATA_WIDTH | 32
TIMING_TIS | 200
TIMING_TIH | 275
TIMING_TDS | 75
TIMING_TDH | 150
TIMING_TDQSQ | 200
TIMING_TQH | 0.38
TIMING_TDQSCK | 400
TIMING_TDQSCKDS | 450
TIMING_TDQSCKDM | 900
TIMING_TDQSCKDL | 1200
TIMING_TDQSS | 0.25
TIMING_TQSH | 0.38
TIMING_TDSH | 0.2
TIMING_TDSS | 0.2
MEM_TINIT_US | 500
MEM_TINIT_CK | 150000
MEM_TDQSCK | 1
MEM_TMRD_CK | 4
MEM_TRAS_NS | 37.5
MEM_TRCD_NS | 15.0
MEM_TRP_NS | 15.0
MEM_TREFI_US | 7.8
MEM_TRFC_NS | 300.0
CFG_TCCD_NS | 2.5
MEM_TWR_NS | 15.0
MEM_TWTR | 4
MEM_TFAW_NS | 50.0
MEM_TRRD_NS | 13.2
MEM_TRTP_NS | 13.2
RATE | Half
MEM_CLK_FREQ | 300.0
USE_MEM_CLK_FREQ | false
USE_DQS_TRACKING | false
FORCE_DQS_TRACKING | AUTO
USE_HPS_DQS_TRACKING | false
USE_SHADOW_REGS | false
FORCE_SHADOW_REGS | AUTO
DQ_DDR | 1
ADDR_CMD_DDR | 0
AFI_RATE_RATIO | 2
DATA_RATE_RATIO | 2
ADDR_RATE_RATIO | 1
AFI_ADDR_WIDTH | 30
AFI_BANKADDR_WIDTH | 6
AFI_CONTROL_WIDTH | 2
AFI_CS_WIDTH | 2
AFI_CLK_EN_WIDTH | 2
AFI_DM_WIDTH | 16
AFI_DQ_WIDTH | 128
AFI_ODT_WIDTH | 2
AFI_WRITE_DQS_WIDTH | 8
AFI_RLAT_WIDTH | 6
AFI_WLAT_WIDTH | 6
AFI_RRANK_WIDTH | 8
AFI_WRANK_WIDTH | 8
AFI_CLK_PAIR_COUNT | 1
MRS_MIRROR_PING_PONG_ATSO | false
SYS_INFO_DEVICE_FAMILY | CYCLONEV
PARSE_FRIENDLY_DEVICE_FAMILY | CYCLONEV
DEVICE_FAMILY | Cyclone V
PRE_V_SERIES_FAMILY | false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID | true
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID | false
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM |
DEVICE_FAMILY_PARAM |
SPEED_GRADE | 8
IS_ES_DEVICE | false
DISABLE_CHILD_MESSAGING | false
HARD_PHY | false
HARD_EMIF | false
HHP_HPS | false
HHP_HPS_VERIFICATION | false
HHP_HPS_SIMULATION | false
HPS_PROTOCOL | DEFAULT
CUT_NEW_FAMILY_TIMING | true
EXPORT_CSR_PORT | false
CSR_ADDR_WIDTH | 8
CSR_DATA_WIDTH | 32
CSR_BE_WIDTH | 4
CTL_CS_WIDTH | 1
AVL_ADDR_WIDTH | 26
AVL_BE_WIDTH | 16
AVL_DATA_WIDTH | 128
AVL_SYMBOL_WIDTH | 8
AVL_NUM_SYMBOLS | 16
AVL_SIZE_WIDTH | 3
HR_DDIO_OUT_HAS_THREE_REGS | false
CTL_ECC_CSR_ENABLED | false
DWIDTH_RATIO | 4
CTL_ODT_ENABLED | true
CTL_OUTPUT_REGD | false
CTL_ECC_MULTIPLES_40_72 | 1
CTL_ECC_MULTIPLES_16_24_40_72 | 1
CTL_REGDIMM_ENABLED | false
LOW_LATENCY | false
CONTROLLER_TYPE | nextgen_v110
CTL_TBP_NUM | 4
CTL_USR_REFRESH | 0
CTL_SELF_REFRESH | 0
CFG_TYPE | 2
CFG_INTERFACE_WIDTH | 32
CFG_BURST_LENGTH | 8
CFG_ADDR_ORDER | 0
CFG_PDN_EXIT_CYCLES | 10
CFG_POWER_SAVING_EXIT_CYCLES | 5
CFG_MEM_CLK_ENTRY_CYCLES | 20
CFG_SELF_RFSH_EXIT_CYCLES | 512
CFG_PORT_WIDTH_WRITE_ODT_CHIP | 1
CFG_PORT_WIDTH_READ_ODT_CHIP | 1
CFG_WRITE_ODT_CHIP | 1
CFG_READ_ODT_CHIP | 0
LOCAL_CS_WIDTH | 0
CFG_CLR_INTR | 0
CFG_ENABLE_NO_DM | 0
MEM_ADD_LAT | 0
CTL_ENABLE_BURST_INTERRUPT_INT | false
CTL_ENABLE_BURST_TERMINATE_INT | false
CFG_ERRCMD_FIFO_REG | 0
CFG_ECC_DECODER_REG | 0
CTL_ENABLE_WDATA_PATH_LATENCY | false
CFG_STARVE_LIMIT | 10
MEM_AUTO_PD_CYCLES | 0
AVL_PORT |
AVL_DATA_WIDTH_PORT_0 | 0
AVL_ADDR_WIDTH_PORT_0 | 0
PRIORITY_PORT_0 | 0
WEIGHT_PORT_0 | 0
CPORT_TYPE_PORT_0 | 0
AVL_NUM_SYMBOLS_PORT_0 | 2
LSB_WFIFO_PORT_0 | 5
MSB_WFIFO_PORT_0 | 5
LSB_RFIFO_PORT_0 | 5
MSB_RFIFO_PORT_0 | 5
AVL_DATA_WIDTH_PORT_1 | 0
AVL_ADDR_WIDTH_PORT_1 | 0
PRIORITY_PORT_1 | 0
WEIGHT_PORT_1 | 0
CPORT_TYPE_PORT_1 | 0
AVL_NUM_SYMBOLS_PORT_1 | 2
LSB_WFIFO_PORT_1 | 5
MSB_WFIFO_PORT_1 | 5
LSB_RFIFO_PORT_1 | 5
MSB_RFIFO_PORT_1 | 5
AVL_DATA_WIDTH_PORT_2 | 0
AVL_ADDR_WIDTH_PORT_2 | 0
PRIORITY_PORT_2 | 0
WEIGHT_PORT_2 | 0
CPORT_TYPE_PORT_2 | 0
AVL_NUM_SYMBOLS_PORT_2 | 2
LSB_WFIFO_PORT_2 | 5
MSB_WFIFO_PORT_2 | 5
LSB_RFIFO_PORT_2 | 5
MSB_RFIFO_PORT_2 | 5
AVL_DATA_WIDTH_PORT_3 | 0
AVL_ADDR_WIDTH_PORT_3 | 0
PRIORITY_PORT_3 | 0
WEIGHT_PORT_3 | 0
CPORT_TYPE_PORT_3 | 0
AVL_NUM_SYMBOLS_PORT_3 | 2
LSB_WFIFO_PORT_3 | 5
MSB_WFIFO_PORT_3 | 5
LSB_RFIFO_PORT_3 | 5
MSB_RFIFO_PORT_3 | 5
AVL_DATA_WIDTH_PORT_4 | 0
AVL_ADDR_WIDTH_PORT_4 | 0
PRIORITY_PORT_4 | 0
WEIGHT_PORT_4 | 0
CPORT_TYPE_PORT_4 | 0
AVL_NUM_SYMBOLS_PORT_4 | 2
LSB_WFIFO_PORT_4 | 5
MSB_WFIFO_PORT_4 | 5
LSB_RFIFO_PORT_4 | 5
MSB_RFIFO_PORT_4 | 5
AVL_DATA_WIDTH_PORT_5 | 0
AVL_ADDR_WIDTH_PORT_5 | 0
PRIORITY_PORT_5 | 0
WEIGHT_PORT_5 | 0
CPORT_TYPE_PORT_5 | 0
AVL_NUM_SYMBOLS_PORT_5 | 2
LSB_WFIFO_PORT_5 | 5
MSB_WFIFO_PORT_5 | 5
LSB_RFIFO_PORT_5 | 5
MSB_RFIFO_PORT_5 | 5
ALLOCATED_RFIFO_PORT | 0,None,None,None,None,None
ALLOCATED_WFIFO_PORT | 0,None,None,None,None,None
ENUM_ATTR_COUNTER_ONE_RESET | DISABLED
ENUM_ATTR_COUNTER_ZERO_RESET | DISABLED
ENUM_ATTR_STATIC_CONFIG_VALID | DISABLED
ENUM_AUTO_PCH_ENABLE_0 | DISABLED
ENUM_AUTO_PCH_ENABLE_1 | DISABLED
ENUM_AUTO_PCH_ENABLE_2 | DISABLED
ENUM_AUTO_PCH_ENABLE_3 | DISABLED
ENUM_AUTO_PCH_ENABLE_4 | DISABLED
ENUM_AUTO_PCH_ENABLE_5 | DISABLED
ENUM_CAL_REQ | DISABLED
ENUM_CFG_BURST_LENGTH | BL_8
ENUM_CFG_INTERFACE_WIDTH | DWIDTH_32
ENUM_CFG_SELF_RFSH_EXIT_CYCLES |
ENUM_CFG_STARVE_LIMIT | STARVE_LIMIT_32
ENUM_CFG_TYPE | DDR3
ENUM_CLOCK_OFF_0 | DISABLED
ENUM_CLOCK_OFF_1 | DISABLED
ENUM_CLOCK_OFF_2 | DISABLED
ENUM_CLOCK_OFF_3 | DISABLED
ENUM_CLOCK_OFF_4 | DISABLED
ENUM_CLOCK_OFF_5 | DISABLED
ENUM_CLR_INTR | NO_CLR_INTR
ENUM_CMD_PORT_IN_USE_0 | FALSE
ENUM_CMD_PORT_IN_USE_1 | FALSE
ENUM_CMD_PORT_IN_USE_2 | FALSE
ENUM_CMD_PORT_IN_USE_3 | FALSE
ENUM_CMD_PORT_IN_USE_4 | FALSE
ENUM_CMD_PORT_IN_USE_5 | FALSE
ENUM_CPORT0_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT0_RFIFO_MAP | FIFO_0
ENUM_CPORT0_TYPE | DISABLE
ENUM_CPORT0_WFIFO_MAP | FIFO_0
ENUM_CPORT1_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT1_RFIFO_MAP | FIFO_0
ENUM_CPORT1_TYPE | DISABLE
ENUM_CPORT1_WFIFO_MAP | FIFO_0
ENUM_CPORT2_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT2_RFIFO_MAP | FIFO_0
ENUM_CPORT2_TYPE | DISABLE
ENUM_CPORT2_WFIFO_MAP | FIFO_0
ENUM_CPORT3_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT3_RFIFO_MAP | FIFO_0
ENUM_CPORT3_TYPE | DISABLE
ENUM_CPORT3_WFIFO_MAP | FIFO_0
ENUM_CPORT4_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT4_RFIFO_MAP | FIFO_0
ENUM_CPORT4_TYPE | DISABLE
ENUM_CPORT4_WFIFO_MAP | FIFO_0
ENUM_CPORT5_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT5_RFIFO_MAP | FIFO_0
ENUM_CPORT5_TYPE | DISABLE
ENUM_CPORT5_WFIFO_MAP | FIFO_0
ENUM_CTL_ADDR_ORDER | CHIP_BANK_ROW_COL
ENUM_CTL_ECC_ENABLED | CTL_ECC_DISABLED
ENUM_CTL_ECC_RMW_ENABLED | CTL_ECC_RMW_DISABLED
ENUM_CTL_REGDIMM_ENABLED | REGDIMM_DISABLED
ENUM_CTL_USR_REFRESH | CTL_USR_REFRESH_DISABLED
ENUM_CTRL_WIDTH | DATA_WIDTH_64_BIT
ENUM_DELAY_BONDING | BONDING_LATENCY_0
ENUM_DFX_BYPASS_ENABLE | DFX_BYPASS_DISABLED
ENUM_DISABLE_MERGING | MERGING_ENABLED
ENUM_ECC_DQ_WIDTH | ECC_DQ_WIDTH_0
ENUM_ENABLE_ATPG | DISABLED
ENUM_ENABLE_BONDING_0 | DISABLED
ENUM_ENABLE_BONDING_1 | DISABLED
ENUM_ENABLE_BONDING_2 | DISABLED
ENUM_ENABLE_BONDING_3 | DISABLED
ENUM_ENABLE_BONDING_4 | DISABLED
ENUM_ENABLE_BONDING_5 | DISABLED
ENUM_ENABLE_BONDING_WRAPBACK | DISABLED
ENUM_ENABLE_DQS_TRACKING | DISABLED
ENUM_ENABLE_ECC_CODE_OVERWRITES | DISABLED
ENUM_ENABLE_FAST_EXIT_PPD | DISABLED
ENUM_ENABLE_INTR | DISABLED
ENUM_ENABLE_NO_DM | DISABLED
ENUM_ENABLE_PIPELINEGLOBAL | DISABLED
ENUM_GANGED_ARF | DISABLED
ENUM_GEN_DBE | GEN_DBE_DISABLED
ENUM_GEN_SBE | GEN_SBE_DISABLED
ENUM_INC_SYNC | FIFO_SET_2
ENUM_LOCAL_IF_CS_WIDTH | ADDR_WIDTH_2
ENUM_MASK_CORR_DROPPED_INTR | DISABLED
ENUM_MASK_DBE_INTR | DISABLED
ENUM_MASK_SBE_INTR | DISABLED
ENUM_MEM_IF_AL | AL_0
ENUM_MEM_IF_BANKADDR_WIDTH | ADDR_WIDTH_3
ENUM_MEM_IF_BURSTLENGTH | MEM_IF_BURSTLENGTH_8
ENUM_MEM_IF_COLADDR_WIDTH | ADDR_WIDTH_12
ENUM_MEM_IF_CS_PER_RANK | MEM_IF_CS_PER_RANK_1
ENUM_MEM_IF_CS_WIDTH | MEM_IF_CS_WIDTH_1
ENUM_MEM_IF_DQ_PER_CHIP | MEM_IF_DQ_PER_CHIP_8
ENUM_MEM_IF_DQS_WIDTH | DQS_WIDTH_4
ENUM_MEM_IF_DWIDTH | MEM_IF_DWIDTH_32
ENUM_MEM_IF_MEMTYPE | DDR3_SDRAM
ENUM_MEM_IF_ROWADDR_WIDTH | ADDR_WIDTH_16
ENUM_MEM_IF_SPEEDBIN | DDR3_1066_6_6_6
ENUM_MEM_IF_TCCD | TCCD_4
ENUM_MEM_IF_TCL | TCL_6
ENUM_MEM_IF_TCWL | TCWL_5
ENUM_MEM_IF_TFAW | TFAW_16
ENUM_MEM_IF_TMRD |
ENUM_MEM_IF_TRAS | TRAS_16
ENUM_MEM_IF_TRC | TRC_22
ENUM_MEM_IF_TRCD | TRCD_6
ENUM_MEM_IF_TRP | TRP_6
ENUM_MEM_IF_TRRD | TRRD_4
ENUM_MEM_IF_TRTP | TRTP_4
ENUM_MEM_IF_TWR | TWR_6
ENUM_MEM_IF_TWTR | TWTR_4
ENUM_MMR_CFG_MEM_BL | MP_BL_8
ENUM_OUTPUT_REGD | DISABLED
ENUM_PDN_EXIT_CYCLES | SLOW_EXIT
ENUM_PORT0_WIDTH | PORT_64_BIT
ENUM_PORT1_WIDTH | PORT_64_BIT
ENUM_PORT2_WIDTH | PORT_64_BIT
ENUM_PORT3_WIDTH | PORT_64_BIT
ENUM_PORT4_WIDTH | PORT_64_BIT
ENUM_PORT5_WIDTH | PORT_64_BIT
ENUM_PRIORITY_0_0 | WEIGHT_0
ENUM_PRIORITY_0_1 | WEIGHT_0
ENUM_PRIORITY_0_2 | WEIGHT_0
ENUM_PRIORITY_0_3 | WEIGHT_0
ENUM_PRIORITY_0_4 | WEIGHT_0
ENUM_PRIORITY_0_5 | WEIGHT_0
ENUM_PRIORITY_1_0 | WEIGHT_0
ENUM_PRIORITY_1_1 | WEIGHT_0
ENUM_PRIORITY_1_2 | WEIGHT_0
ENUM_PRIORITY_1_3 | WEIGHT_0
ENUM_PRIORITY_1_4 | WEIGHT_0
ENUM_PRIORITY_1_5 | WEIGHT_0
ENUM_PRIORITY_2_0 | WEIGHT_0
ENUM_PRIORITY_2_1 | WEIGHT_0
ENUM_PRIORITY_2_2 | WEIGHT_0
ENUM_PRIORITY_2_3 | WEIGHT_0
ENUM_PRIORITY_2_4 | WEIGHT_0
ENUM_PRIORITY_2_5 | WEIGHT_0
ENUM_PRIORITY_3_0 | WEIGHT_0
ENUM_PRIORITY_3_1 | WEIGHT_0
ENUM_PRIORITY_3_2 | WEIGHT_0
ENUM_PRIORITY_3_3 | WEIGHT_0
ENUM_PRIORITY_3_4 | WEIGHT_0
ENUM_PRIORITY_3_5 | WEIGHT_0
ENUM_PRIORITY_4_0 | WEIGHT_0
ENUM_PRIORITY_4_1 | WEIGHT_0
ENUM_PRIORITY_4_2 | WEIGHT_0
ENUM_PRIORITY_4_3 | WEIGHT_0
ENUM_PRIORITY_4_4 | WEIGHT_0
ENUM_PRIORITY_4_5 | WEIGHT_0
ENUM_PRIORITY_5_0 | WEIGHT_0
ENUM_PRIORITY_5_1 | WEIGHT_0
ENUM_PRIORITY_5_2 | WEIGHT_0
ENUM_PRIORITY_5_3 | WEIGHT_0
ENUM_PRIORITY_5_4 | WEIGHT_0
ENUM_PRIORITY_5_5 | WEIGHT_0
ENUM_PRIORITY_6_0 | WEIGHT_0
ENUM_PRIORITY_6_1 | WEIGHT_0
ENUM_PRIORITY_6_2 | WEIGHT_0
ENUM_PRIORITY_6_3 | WEIGHT_0
ENUM_PRIORITY_6_4 | WEIGHT_0
ENUM_PRIORITY_6_5 | WEIGHT_0
ENUM_PRIORITY_7_0 | WEIGHT_0
ENUM_PRIORITY_7_1 | WEIGHT_0
ENUM_PRIORITY_7_2 | WEIGHT_0
ENUM_PRIORITY_7_3 | WEIGHT_0
ENUM_PRIORITY_7_4 | WEIGHT_0
ENUM_PRIORITY_7_5 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_0 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_1 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_2 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_3 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_4 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_5 | WEIGHT_0
ENUM_RCFG_USER_PRIORITY_0 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_1 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_2 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_3 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_4 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_5 | PRIORITY_0
ENUM_RD_DWIDTH_0 | DWIDTH_0
ENUM_RD_DWIDTH_1 | DWIDTH_0
ENUM_RD_DWIDTH_2 | DWIDTH_0
ENUM_RD_DWIDTH_3 | DWIDTH_0
ENUM_RD_DWIDTH_4 | DWIDTH_0
ENUM_RD_DWIDTH_5 | DWIDTH_0
ENUM_RD_FIFO_IN_USE_0 | FALSE
ENUM_RD_FIFO_IN_USE_1 | FALSE
ENUM_RD_FIFO_IN_USE_2 | FALSE
ENUM_RD_FIFO_IN_USE_3 | FALSE
ENUM_RD_PORT_INFO_0 | USE_NO
ENUM_RD_PORT_INFO_1 | USE_NO
ENUM_RD_PORT_INFO_2 | USE_NO
ENUM_RD_PORT_INFO_3 | USE_NO
ENUM_RD_PORT_INFO_4 | USE_NO
ENUM_RD_PORT_INFO_5 | USE_NO
ENUM_READ_ODT_CHIP | ODT_DISABLED
ENUM_REORDER_DATA | DATA_REORDERING
ENUM_RFIFO0_CPORT_MAP | CMD_PORT_0
ENUM_RFIFO1_CPORT_MAP | CMD_PORT_0
ENUM_RFIFO2_CPORT_MAP | CMD_PORT_0
ENUM_RFIFO3_CPORT_MAP | CMD_PORT_0
ENUM_SINGLE_READY_0 | CONCATENATE_RDY
ENUM_SINGLE_READY_1 | CONCATENATE_RDY
ENUM_SINGLE_READY_2 | CONCATENATE_RDY
ENUM_SINGLE_READY_3 | CONCATENATE_RDY
ENUM_STATIC_WEIGHT_0 | WEIGHT_0
ENUM_STATIC_WEIGHT_1 | WEIGHT_0
ENUM_STATIC_WEIGHT_2 | WEIGHT_0
ENUM_STATIC_WEIGHT_3 | WEIGHT_0
ENUM_STATIC_WEIGHT_4 | WEIGHT_0
ENUM_STATIC_WEIGHT_5 | WEIGHT_0
ENUM_SYNC_MODE_0 | ASYNCHRONOUS
ENUM_SYNC_MODE_1 | ASYNCHRONOUS
ENUM_SYNC_MODE_2 | ASYNCHRONOUS
ENUM_SYNC_MODE_3 | ASYNCHRONOUS
ENUM_SYNC_MODE_4 | ASYNCHRONOUS
ENUM_SYNC_MODE_5 | ASYNCHRONOUS
ENUM_TEST_MODE | NORMAL_MODE
ENUM_THLD_JAR1_0 | THRESHOLD_32
ENUM_THLD_JAR1_1 | THRESHOLD_32
ENUM_THLD_JAR1_2 | THRESHOLD_32
ENUM_THLD_JAR1_3 | THRESHOLD_32
ENUM_THLD_JAR1_4 | THRESHOLD_32
ENUM_THLD_JAR1_5 | THRESHOLD_32
ENUM_THLD_JAR2_0 | THRESHOLD_16
ENUM_THLD_JAR2_1 | THRESHOLD_16
ENUM_THLD_JAR2_2 | THRESHOLD_16
ENUM_THLD_JAR2_3 | THRESHOLD_16
ENUM_THLD_JAR2_4 | THRESHOLD_16
ENUM_THLD_JAR2_5 | THRESHOLD_16
ENUM_USE_ALMOST_EMPTY_0 | EMPTY
ENUM_USE_ALMOST_EMPTY_1 | EMPTY
ENUM_USE_ALMOST_EMPTY_2 | EMPTY
ENUM_USE_ALMOST_EMPTY_3 | EMPTY
ENUM_USER_ECC_EN | DISABLE
ENUM_USER_PRIORITY_0 | PRIORITY_0
ENUM_USER_PRIORITY_1 | PRIORITY_0
ENUM_USER_PRIORITY_2 | PRIORITY_0
ENUM_USER_PRIORITY_3 | PRIORITY_0
ENUM_USER_PRIORITY_4 | PRIORITY_0
ENUM_USER_PRIORITY_5 | PRIORITY_0
ENUM_WFIFO0_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO0_RDY_ALMOST_FULL | NOT_FULL
ENUM_WFIFO1_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO1_RDY_ALMOST_FULL | NOT_FULL
ENUM_WFIFO2_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO2_RDY_ALMOST_FULL | NOT_FULL
ENUM_WFIFO3_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO3_RDY_ALMOST_FULL | NOT_FULL
ENUM_WR_DWIDTH_0 | DWIDTH_0
ENUM_WR_DWIDTH_1 | DWIDTH_0
ENUM_WR_DWIDTH_2 | DWIDTH_0
ENUM_WR_DWIDTH_3 | DWIDTH_0
ENUM_WR_DWIDTH_4 | DWIDTH_0
ENUM_WR_DWIDTH_5 | DWIDTH_0
ENUM_WR_FIFO_IN_USE_0 | FALSE
ENUM_WR_FIFO_IN_USE_1 | FALSE
ENUM_WR_FIFO_IN_USE_2 | FALSE
ENUM_WR_FIFO_IN_USE_3 | FALSE
ENUM_WR_PORT_INFO_0 | USE_NO
ENUM_WR_PORT_INFO_1 | USE_NO
ENUM_WR_PORT_INFO_2 | USE_NO
ENUM_WR_PORT_INFO_3 | USE_NO
ENUM_WR_PORT_INFO_4 | USE_NO
ENUM_WR_PORT_INFO_5 | USE_NO
ENUM_WRITE_ODT_CHIP | ODT_DISABLED
INTG_MEM_AUTO_PD_CYCLES | 0
INTG_CYC_TO_RLD_JARS_0 | 1
INTG_CYC_TO_RLD_JARS_1 | 1
INTG_CYC_TO_RLD_JARS_2 | 1
INTG_CYC_TO_RLD_JARS_3 | 1
INTG_CYC_TO_RLD_JARS_4 | 1
INTG_CYC_TO_RLD_JARS_5 | 1
INTG_EXTRA_CTL_CLK_ACT_TO_ACT | 0
INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK | 0
INTG_EXTRA_CTL_CLK_ACT_TO_PCH | 0
INTG_EXTRA_CTL_CLK_ACT_TO_RDWR | 0
INTG_EXTRA_CTL_CLK_ARF_PERIOD | 0
INTG_EXTRA_CTL_CLK_ARF_TO_VALID | 0
INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT | 0
INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID | 0
INTG_EXTRA_CTL_CLK_PCH_TO_VALID | 0
INTG_EXTRA_CTL_CLK_PDN_PERIOD | 0
INTG_EXTRA_CTL_CLK_PDN_TO_VALID | 0
INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID | 0
INTG_EXTRA_CTL_CLK_RD_TO_PCH | 0
INTG_EXTRA_CTL_CLK_RD_TO_RD | 0
INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP | 0
INTG_EXTRA_CTL_CLK_RD_TO_WR | 0
INTG_EXTRA_CTL_CLK_RD_TO_WR_BC | 0
INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP | 0
INTG_EXTRA_CTL_CLK_SRF_TO_VALID | 0
INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL | 0
INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID | 0
INTG_EXTRA_CTL_CLK_WR_TO_PCH | 0
INTG_EXTRA_CTL_CLK_WR_TO_RD | 0
INTG_EXTRA_CTL_CLK_WR_TO_RD_BC | 0
INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP | 0
INTG_EXTRA_CTL_CLK_WR_TO_WR | 0
INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP | 0
INTG_MEM_IF_TREFI | 3120
INTG_MEM_IF_TRFC | 34
INTG_RCFG_SUM_WT_PRIORITY_0 | 0
INTG_RCFG_SUM_WT_PRIORITY_1 | 0
INTG_RCFG_SUM_WT_PRIORITY_2 | 0
INTG_RCFG_SUM_WT_PRIORITY_3 | 0
INTG_RCFG_SUM_WT_PRIORITY_4 | 0
INTG_RCFG_SUM_WT_PRIORITY_5 | 0
INTG_RCFG_SUM_WT_PRIORITY_6 | 0
INTG_RCFG_SUM_WT_PRIORITY_7 | 0
INTG_SUM_WT_PRIORITY_0 | 0
INTG_SUM_WT_PRIORITY_1 | 0
INTG_SUM_WT_PRIORITY_2 | 0
INTG_SUM_WT_PRIORITY_3 | 0
INTG_SUM_WT_PRIORITY_4 | 0
INTG_SUM_WT_PRIORITY_5 | 0
INTG_SUM_WT_PRIORITY_6 | 0
INTG_SUM_WT_PRIORITY_7 | 0
VECT_ATTR_COUNTER_ONE_MASK | 0
VECT_ATTR_COUNTER_ONE_MATCH | 0
VECT_ATTR_COUNTER_ZERO_MASK | 0
VECT_ATTR_COUNTER_ZERO_MATCH | 0
VECT_ATTR_DEBUG_SELECT_BYTE | 0
INTG_POWER_SAVING_EXIT_CYCLES | 5
INTG_MEM_CLK_ENTRY_CYCLES | 10
ENUM_ENABLE_BURST_INTERRUPT | DISABLED
ENUM_ENABLE_BURST_TERMINATE | DISABLED
POWER_OF_TWO_BUS | false
SOPC_COMPAT_RESET | false
AVL_MAX_SIZE | 4
BYTE_ENABLE | true
ENABLE_CTRL_AVALON_INTERFACE | true
CTL_DEEP_POWERDN_EN | false
CTL_SELF_REFRESH_EN | false
AUTO_POWERDN_EN | false
AUTO_PD_CYCLES | 0
CTL_USR_REFRESH_EN | false
CTL_AUTOPCH_EN | false
CTL_ZQCAL_EN | false
ADDR_ORDER | 0
CTL_LOOK_AHEAD_DEPTH | 4
CONTROLLER_LATENCY | 5
CFG_REORDER_DATA | true
STARVE_LIMIT | 10
CTL_CSR_ENABLED | false
CTL_CSR_CONNECTION | INTERNAL_JTAG
CTL_ECC_ENABLED | false
CTL_HRB_ENABLED | false
CTL_ECC_AUTO_CORRECTION_ENABLED | false
MULTICAST_EN | false
CTL_DYNAMIC_BANK_ALLOCATION | false
CTL_DYNAMIC_BANK_NUM | 4
DEBUG_MODE | false
ENABLE_BURST_MERGE | false
CTL_ENABLE_BURST_INTERRUPT | true
CTL_ENABLE_BURST_TERMINATE | true
LOCAL_ID_WIDTH | 8
RDBUFFER_ADDR_WIDTH | 7
WRBUFFER_ADDR_WIDTH | 6
MAX_PENDING_WR_CMD | 8
MAX_PENDING_RD_CMD | 16
USE_MM_ADAPTOR | true
USE_AXI_ADAPTOR | false
HCX_COMPAT_MODE | false
CTL_CMD_QUEUE_DEPTH | 8
CTL_CSR_READ_ONLY | 1
CFG_DATA_REORDERING_TYPE | INTER_BANK
NUM_OF_PORTS | 1
ENABLE_BONDING | false
ENABLE_USER_ECC | false
AVL_DATA_WIDTH_PORT | 32,32,32,32,32,32
PRIORITY_PORT | 1,1,1,1,1,1
WEIGHT_PORT | 0,0,0,0,0,0
CPORT_TYPE_PORT | Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional
CORE_PERIPHERY_DUAL_CLOCK | false
USE_DR_CLK | false
DLL_USE_DR_CLK | false
USE_2X_FF | false
DUAL_WRITE_CLOCK | false
GENERIC_PLL | true
USE_HARD_READ_FIFO | false
READ_FIFO_HALF_RATE | true
PLL_MASTER | true
DLL_MASTER | true
PHY_VERSION_NUMBER | 130
ENABLE_NIOS_OCI | false
ENABLE_EMIT_JTAG_MASTER | true
ENABLE_NIOS_JTAG_UART | false
ENABLE_NIOS_PRINTF_OUTPUT | false
ENABLE_LARGE_RW_MGR_DI_BUFFER | false
ENABLE_EMIT_BFM_MASTER | false
FORCE_SEQUENCER_TCL_DEBUG_MODE | false
ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT | false
ENABLE_MAX_SIZE_SEQ_MEM | false
MAKE_INTERNAL_NIOS_VISIBLE | false
DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG | false
ENABLE_CSR_SOFT_RESET_REQ | true
DUPLICATE_PLL_FOR_PHY_CLK | true
MAX_LATENCY_COUNT_WIDTH | 5
READ_VALID_FIFO_SIZE | 16
EXTRA_VFIFO_SHIFT | 0
TB_MEM_CLK_FREQ | 300.0
TB_RATE | HALF
TB_MEM_IF_DQ_WIDTH | 32
TB_MEM_IF_READ_DQS_WIDTH | 4
TB_PLL_DLL_MASTER | true
FAST_SIM_CALIBRATION | false
REF_CLK_FREQ | 50.0
REF_CLK_FREQ_STR | 50.0 MHz
REF_CLK_NS | 20.0
REF_CLK_PS | 20000.0
PLL_DR_CLK_FREQ | 0.0
PLL_DR_CLK_FREQ_STR |
PLL_DR_CLK_FREQ_SIM_STR | 0 ps
PLL_DR_CLK_PHASE_PS | 0
PLL_DR_CLK_PHASE_PS_STR |
PLL_DR_CLK_PHASE_DEG | 0
PLL_DR_CLK_PHASE_PS_SIM | 0
PLL_DR_CLK_PHASE_PS_SIM_STR |
PLL_DR_CLK_PHASE_DEG_SIM | 0
PLL_DR_CLK_MULT | 0
PLL_DR_CLK_DIV | 0
PLL_MEM_CLK_FREQ | 300.0
PLL_MEM_CLK_FREQ_STR | 300.0 MHz
PLL_MEM_CLK_FREQ_SIM_STR | 3334 ps
PLL_MEM_CLK_PHASE_PS | 0
PLL_MEM_CLK_PHASE_PS_STR | 0 ps
PLL_MEM_CLK_PHASE_DEG | 0
PLL_MEM_CLK_PHASE_PS_SIM | 0
PLL_MEM_CLK_PHASE_PS_SIM_STR | 0 ps
PLL_MEM_CLK_PHASE_DEG_SIM | 0
PLL_MEM_CLK_MULT | 6000000
PLL_MEM_CLK_DIV | 1000000
PLL_AFI_CLK_FREQ | 150.0
PLL_AFI_CLK_FREQ_STR | 150.0 MHz
PLL_AFI_CLK_FREQ_SIM_STR | 6668 ps
PLL_AFI_CLK_PHASE_PS | 0
PLL_AFI_CLK_PHASE_PS_STR | 0 ps
PLL_AFI_CLK_PHASE_DEG | 0
PLL_AFI_CLK_PHASE_PS_SIM | 0
PLL_AFI_CLK_PHASE_PS_SIM_STR | 0 ps
PLL_AFI_CLK_PHASE_DEG_SIM | 0
PLL_AFI_CLK_MULT | 6000000
PLL_AFI_CLK_DIV | 2000000
PLL_WRITE_CLK_FREQ | 300.0
PLL_WRITE_CLK_FREQ_STR | 300.0 MHz
PLL_WRITE_CLK_FREQ_SIM_STR | 3334 ps
PLL_WRITE_CLK_PHASE_PS | 2500
PLL_WRITE_CLK_PHASE_PS_STR | 2500 ps
PLL_WRITE_CLK_PHASE_DEG | 270
PLL_WRITE_CLK_PHASE_PS_SIM | 2500
PLL_WRITE_CLK_PHASE_PS_SIM_STR | 2500 ps
PLL_WRITE_CLK_PHASE_DEG_SIM | 270
PLL_WRITE_CLK_MULT | 6000000
PLL_WRITE_CLK_DIV | 1000000
PLL_ADDR_CMD_CLK_FREQ | 150.0
PLL_ADDR_CMD_CLK_FREQ_STR | 150.0 MHz
PLL_ADDR_CMD_CLK_FREQ_SIM_STR | 6668 ps
PLL_ADDR_CMD_CLK_PHASE_PS | 4583
PLL_ADDR_CMD_CLK_PHASE_PS_STR | 4583 ps
PLL_ADDR_CMD_CLK_PHASE_DEG | 247
PLL_ADDR_CMD_CLK_PHASE_PS_SIM | 4574
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR | 4574 ps
PLL_ADDR_CMD_CLK_PHASE_DEG_SIM | 247
PLL_ADDR_CMD_CLK_MULT | 6000000
PLL_ADDR_CMD_CLK_DIV | 2000000
PLL_AFI_HALF_CLK_FREQ | 75.0
PLL_AFI_HALF_CLK_FREQ_STR | 75.0 MHz
PLL_AFI_HALF_CLK_FREQ_SIM_STR | 13336 ps
PLL_AFI_HALF_CLK_PHASE_PS | 0
PLL_AFI_HALF_CLK_PHASE_PS_STR | 0 ps
PLL_AFI_HALF_CLK_PHASE_DEG | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR | 0 ps
PLL_AFI_HALF_CLK_PHASE_DEG_SIM | 0
PLL_AFI_HALF_CLK_MULT | 6000000
PLL_AFI_HALF_CLK_DIV | 4000000
PLL_NIOS_CLK_FREQ | 75.0
PLL_NIOS_CLK_FREQ_STR | 75.0 MHz
PLL_NIOS_CLK_FREQ_SIM_STR | 13336 ps
PLL_NIOS_CLK_PHASE_PS | 0
PLL_NIOS_CLK_PHASE_PS_STR | 0 ps
PLL_NIOS_CLK_PHASE_DEG | 0
PLL_NIOS_CLK_PHASE_PS_SIM | 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR | 0 ps
PLL_NIOS_CLK_PHASE_DEG_SIM | 0
PLL_NIOS_CLK_MULT | 6000000
PLL_NIOS_CLK_DIV | 4000000
PLL_CONFIG_CLK_FREQ | 25.0
PLL_CONFIG_CLK_FREQ_STR | 25.0 MHz
PLL_CONFIG_CLK_FREQ_SIM_STR | 40008 ps
PLL_CONFIG_CLK_PHASE_PS | 0
PLL_CONFIG_CLK_PHASE_PS_STR | 0 ps
PLL_CONFIG_CLK_PHASE_DEG | 0
PLL_CONFIG_CLK_PHASE_PS_SIM | 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR | 0 ps
PLL_CONFIG_CLK_PHASE_DEG_SIM | 0
PLL_CONFIG_CLK_MULT | 6000000
PLL_CONFIG_CLK_DIV | 12000000
PLL_P2C_READ_CLK_FREQ | 0.0
PLL_P2C_READ_CLK_FREQ_STR |
PLL_P2C_READ_CLK_FREQ_SIM_STR | 0 ps
PLL_P2C_READ_CLK_PHASE_PS | 0
PLL_P2C_READ_CLK_PHASE_PS_STR |
PLL_P2C_READ_CLK_PHASE_DEG | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR |
PLL_P2C_READ_CLK_PHASE_DEG_SIM | 0
PLL_P2C_READ_CLK_MULT | 0
PLL_P2C_READ_CLK_DIV | 0
PLL_C2P_WRITE_CLK_FREQ | 0.0
PLL_C2P_WRITE_CLK_FREQ_STR |
PLL_C2P_WRITE_CLK_FREQ_SIM_STR | 0 ps
PLL_C2P_WRITE_CLK_PHASE_PS | 0
PLL_C2P_WRITE_CLK_PHASE_PS_STR |
PLL_C2P_WRITE_CLK_PHASE_DEG | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR |
PLL_C2P_WRITE_CLK_PHASE_DEG_SIM | 0
PLL_C2P_WRITE_CLK_MULT | 0
PLL_C2P_WRITE_CLK_DIV | 0
PLL_HR_CLK_FREQ | 0.0
PLL_HR_CLK_FREQ_STR |
PLL_HR_CLK_FREQ_SIM_STR | 0 ps
PLL_HR_CLK_PHASE_PS | 0
PLL_HR_CLK_PHASE_PS_STR |
PLL_HR_CLK_PHASE_DEG | 0
PLL_HR_CLK_PHASE_PS_SIM | 0
PLL_HR_CLK_PHASE_PS_SIM_STR |
PLL_HR_CLK_PHASE_DEG_SIM | 0
PLL_HR_CLK_MULT | 0
PLL_HR_CLK_DIV | 0
PLL_AFI_PHY_CLK_FREQ | 150.0
PLL_AFI_PHY_CLK_FREQ_STR | 150.0 MHz
PLL_AFI_PHY_CLK_FREQ_SIM_STR | 6668 ps
PLL_AFI_PHY_CLK_PHASE_PS | 0
PLL_AFI_PHY_CLK_PHASE_PS_STR | 0 ps
PLL_AFI_PHY_CLK_PHASE_DEG | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR | 0 ps
PLL_AFI_PHY_CLK_PHASE_DEG_SIM | 0
PLL_AFI_PHY_CLK_MULT | 6000000
PLL_AFI_PHY_CLK_DIV | 2000000
REF_CLK_FREQ_CACHE_VALID | true
REF_CLK_FREQ_PARAM_VALID | false
REF_CLK_FREQ_MIN_PARAM | 0.0
REF_CLK_FREQ_MAX_PARAM | 0.0
REF_CLK_FREQ_MIN_CACHE | 10.0
REF_CLK_FREQ_MAX_CACHE | 500.0
PLL_DR_CLK_FREQ_PARAM | 0.0
PLL_DR_CLK_FREQ_SIM_STR_PARAM |
PLL_DR_CLK_PHASE_PS_PARAM | 0
PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_DR_CLK_MULT_PARAM | 0
PLL_DR_CLK_DIV_PARAM | 0
PLL_DR_CLK_FREQ_CACHE | 0.0
PLL_DR_CLK_FREQ_SIM_STR_CACHE |
PLL_DR_CLK_PHASE_PS_CACHE | 0
PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_DR_CLK_MULT_CACHE | 0
PLL_DR_CLK_DIV_CACHE | 0
PLL_MEM_CLK_FREQ_PARAM | 0.0
PLL_MEM_CLK_FREQ_SIM_STR_PARAM |
PLL_MEM_CLK_PHASE_PS_PARAM | 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_MEM_CLK_MULT_PARAM | 0
PLL_MEM_CLK_DIV_PARAM | 0
PLL_MEM_CLK_FREQ_CACHE | 300.0
PLL_MEM_CLK_FREQ_SIM_STR_CACHE | 3334 ps
PLL_MEM_CLK_PHASE_PS_CACHE | 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE | 0 ps
PLL_MEM_CLK_MULT_CACHE | 6000000
PLL_MEM_CLK_DIV_CACHE | 1000000
PLL_AFI_CLK_FREQ_PARAM | 0.0
PLL_AFI_CLK_FREQ_SIM_STR_PARAM |
PLL_AFI_CLK_PHASE_PS_PARAM | 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_AFI_CLK_MULT_PARAM | 0
PLL_AFI_CLK_DIV_PARAM | 0
PLL_AFI_CLK_FREQ_CACHE | 150.0
PLL_AFI_CLK_FREQ_SIM_STR_CACHE | 6668 ps
PLL_AFI_CLK_PHASE_PS_CACHE | 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE | 0 ps
PLL_AFI_CLK_MULT_CACHE | 6000000
PLL_AFI_CLK_DIV_CACHE | 2000000
PLL_WRITE_CLK_FREQ_PARAM | 0.0
PLL_WRITE_CLK_FREQ_SIM_STR_PARAM |
PLL_WRITE_CLK_PHASE_PS_PARAM | 0
PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_WRITE_CLK_MULT_PARAM | 0
PLL_WRITE_CLK_DIV_PARAM | 0
PLL_WRITE_CLK_FREQ_CACHE | 300.0
PLL_WRITE_CLK_FREQ_SIM_STR_CACHE | 3334 ps
PLL_WRITE_CLK_PHASE_PS_CACHE | 2500
PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE | 2500 ps
PLL_WRITE_CLK_MULT_CACHE | 6000000
PLL_WRITE_CLK_DIV_CACHE | 1000000
PLL_ADDR_CMD_CLK_FREQ_PARAM | 0.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM |
PLL_ADDR_CMD_CLK_PHASE_PS_PARAM | 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_ADDR_CMD_CLK_MULT_PARAM | 0
PLL_ADDR_CMD_CLK_DIV_PARAM | 0
PLL_ADDR_CMD_CLK_FREQ_CACHE | 150.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE | 6668 ps
PLL_ADDR_CMD_CLK_PHASE_PS_CACHE | 4583
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE | 4574 ps
PLL_ADDR_CMD_CLK_MULT_CACHE | 6000000
PLL_ADDR_CMD_CLK_DIV_CACHE | 2000000
PLL_AFI_HALF_CLK_FREQ_PARAM | 0.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM |
PLL_AFI_HALF_CLK_PHASE_PS_PARAM | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_AFI_HALF_CLK_MULT_PARAM | 0
PLL_AFI_HALF_CLK_DIV_PARAM | 0
PLL_AFI_HALF_CLK_FREQ_CACHE | 75.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE | 13336 ps
PLL_AFI_HALF_CLK_PHASE_PS_CACHE | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE | 0 ps
PLL_AFI_HALF_CLK_MULT_CACHE | 6000000
PLL_AFI_HALF_CLK_DIV_CACHE | 4000000
PLL_NIOS_CLK_FREQ_PARAM | 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_PARAM |
PLL_NIOS_CLK_PHASE_PS_PARAM | 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_NIOS_CLK_MULT_PARAM | 0
PLL_NIOS_CLK_DIV_PARAM | 0
PLL_NIOS_CLK_FREQ_CACHE | 75.0
PLL_NIOS_CLK_FREQ_SIM_STR_CACHE | 13336 ps
PLL_NIOS_CLK_PHASE_PS_CACHE | 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE | 0 ps
PLL_NIOS_CLK_MULT_CACHE | 6000000
PLL_NIOS_CLK_DIV_CACHE | 4000000
PLL_CONFIG_CLK_FREQ_PARAM | 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM |
PLL_CONFIG_CLK_PHASE_PS_PARAM | 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_CONFIG_CLK_MULT_PARAM | 0
PLL_CONFIG_CLK_DIV_PARAM | 0
PLL_CONFIG_CLK_FREQ_CACHE | 25.0
PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE | 40008 ps
PLL_CONFIG_CLK_PHASE_PS_CACHE | 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE | 0 ps
PLL_CONFIG_CLK_MULT_CACHE | 6000000
PLL_CONFIG_CLK_DIV_CACHE | 12000000
PLL_P2C_READ_CLK_FREQ_PARAM | 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM |
PLL_P2C_READ_CLK_PHASE_PS_PARAM | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_P2C_READ_CLK_MULT_PARAM | 0
PLL_P2C_READ_CLK_DIV_PARAM | 0
PLL_P2C_READ_CLK_FREQ_CACHE | 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE |
PLL_P2C_READ_CLK_PHASE_PS_CACHE | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_P2C_READ_CLK_MULT_CACHE | 0
PLL_P2C_READ_CLK_DIV_CACHE | 0
PLL_C2P_WRITE_CLK_FREQ_PARAM | 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM |
PLL_C2P_WRITE_CLK_PHASE_PS_PARAM | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_C2P_WRITE_CLK_MULT_PARAM | 0
PLL_C2P_WRITE_CLK_DIV_PARAM | 0
PLL_C2P_WRITE_CLK_FREQ_CACHE | 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE |
PLL_C2P_WRITE_CLK_PHASE_PS_CACHE | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_C2P_WRITE_CLK_MULT_CACHE | 0
PLL_C2P_WRITE_CLK_DIV_CACHE | 0
PLL_HR_CLK_FREQ_PARAM | 0.0
PLL_HR_CLK_FREQ_SIM_STR_PARAM |
PLL_HR_CLK_PHASE_PS_PARAM | 0
PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_HR_CLK_MULT_PARAM | 0
PLL_HR_CLK_DIV_PARAM | 0
PLL_HR_CLK_FREQ_CACHE | 0.0
PLL_HR_CLK_FREQ_SIM_STR_CACHE |
PLL_HR_CLK_PHASE_PS_CACHE | 0
PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_HR_CLK_MULT_CACHE | 0
PLL_HR_CLK_DIV_CACHE | 0
PLL_AFI_PHY_CLK_FREQ_PARAM | 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM |
PLL_AFI_PHY_CLK_PHASE_PS_PARAM | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_AFI_PHY_CLK_MULT_PARAM | 0
PLL_AFI_PHY_CLK_DIV_PARAM | 0
PLL_AFI_PHY_CLK_FREQ_CACHE | 150.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE | 6668 ps
PLL_AFI_PHY_CLK_PHASE_PS_CACHE | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE | 0 ps
PLL_AFI_PHY_CLK_MULT_CACHE | 6000000
PLL_AFI_PHY_CLK_DIV_CACHE | 2000000
SPEED_GRADE_CACHE | 8
IS_ES_DEVICE_CACHE | false
MEM_CLK_FREQ_CACHE | 300.0
REF_CLK_FREQ_CACHE | 50.0
RATE_CACHE | Half
HCX_COMPAT_MODE_CACHE | false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE | CYCLONEV
COMMAND_PHASE_CACHE | 0.0
MEM_CK_PHASE_CACHE | 0.0
P2C_READ_CLOCK_ADD_PHASE_CACHE | 0.0
C2P_WRITE_CLOCK_ADD_PHASE_CACHE | 0.0
ACV_PHY_CLK_ADD_FR_PHASE_CACHE | 0.0
SEQUENCER_TYPE_CACHE | NIOS
USE_MEM_CLK_FREQ_CACHE | false
PLL_CLK_CACHE_VALID | true
PLL_CLK_PARAM_VALID | false
ENABLE_EXTRA_REPORTING | false
NUM_EXTRA_REPORT_PATH | 10
ENABLE_ISS_PROBES | false
CALIB_REG_WIDTH | 8
USE_SEQUENCER_BFM | false
DEFAULT_FAST_SIM_MODEL | true
PLL_SHARING_MODE | None
NUM_PLL_SHARING_INTERFACES | 1
EXPORT_AFI_HALF_CLK | false
ABSTRACT_REAL_COMPARE_TEST | false
INCLUDE_BOARD_DELAY_MODEL | false
INCLUDE_MULTIRANK_BOARD_DELAY_MODEL | false
USE_FAKE_PHY_INTERNAL | false
USE_FAKE_PHY | false
FORCE_MAX_LATENCY_COUNT_WIDTH | 0
USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE | false
ENABLE_NON_DESTRUCTIVE_CALIB | false
TRACKING_ERROR_TEST | false
TRACKING_WATCH_TEST | false
MARGIN_VARIATION_TEST | false
EXTRA_SETTINGS |
MEM_DEVICE | MISSING_MODEL
FORCE_SYNTHESIS_LANGUAGE |
NUM_SUBGROUP_PER_READ_DQS | 1
QVLD_EXTRA_FLOP_STAGES | 2
QVLD_WR_ADDRESS_OFFSET | 8
MAX_WRITE_LATENCY_COUNT_WIDTH | 4
NUM_WRITE_PATH_FLOP_STAGES | 0
NUM_AC_FR_CYCLE_SHIFTS | 0
FORCED_NUM_WRITE_FR_CYCLE_SHIFTS | 0
NUM_WRITE_FR_CYCLE_SHIFTS | 0
PERFORM_READ_AFTER_WRITE_CALIBRATION | true
SEQ_BURST_COUNT_WIDTH | 1
VCALIB_COUNT_WIDTH | 2
PLL_PHASE_COUNTER_WIDTH | 4
DQS_DELAY_CHAIN_PHASE_SETTING | 2
DQS_PHASE_SHIFT | 9000
DELAYED_CLOCK_PHASE_SETTING | 2
IO_DQS_IN_RESERVE | 4
IO_DQS_OUT_RESERVE | 4
IO_DQ_OUT_RESERVE | 0
IO_DM_OUT_RESERVE | 0
IO_DQS_EN_DELAY_OFFSET | 0
IO_DQS_EN_PHASE_MAX | 7
IO_DQDQS_OUT_PHASE_MAX | 0
IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS | false
MEM_CLK_NS | 3.333
MEM_CLK_PS | 3333.0
CALIB_LFIFO_OFFSET | 6
CALIB_VFIFO_OFFSET | 8
DELAY_PER_OPA_TAP | 416
DELAY_PER_DCHAIN_TAP | 25
DELAY_PER_DQS_EN_DCHAIN_TAP | 25
DQS_EN_DELAY_MAX | 31
DQS_IN_DELAY_MAX | 31
IO_IN_DELAY_MAX | 31
IO_OUT1_DELAY_MAX | 31
IO_OUT2_DELAY_MAX | 0
IO_STANDARD | SSTL-15
VFIFO_AS_SHIFT_REG | false
SEQUENCER_TYPE | NIOS
NIOS_HEX_FILE_LOCATION | ../
ADVERTIZE_SEQUENCER_SW_BUILD_FILES | false
NEGATIVE_WRITE_CK_PHASE | true
MEM_T_WL | 5
MEM_T_RL | 8
PHY_CLKBUF | false
USE_LDC_AS_LOW_SKEW_CLOCK | false
USE_LDC_FOR_ADDR_CMD | false
ENABLE_LDC_MEM_CK_ADJUSTMENT | false
MEM_CK_LDC_ADJUSTMENT_THRESHOLD | 0
LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT | true
LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE | 0
FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT | false
NON_LDC_ADDR_CMD_MEM_CK_INVERT | false
REGISTER_C2P | true
EARLY_ADDR_CMD_CLK_TRANSFER | true
PHY_ONLY | false
SEQ_MODE | 0
ADVANCED_CK_PHASES | false
COMMAND_PHASE | 0.0
MEM_CK_PHASE | 0.0
P2C_READ_CLOCK_ADD_PHASE | 0.0
C2P_WRITE_CLOCK_ADD_PHASE | 0.0
ACV_PHY_CLK_ADD_FR_PHASE | 0.0
MEM_VOLTAGE | 1.5V DDR3
PLL_LOCATION | Top_Bottom
SKIP_MEM_INIT | true
READ_DQ_DQS_CLOCK_SOURCE | INVERTED_DQS_BUS
DQ_INPUT_REG_USE_CLKN | false
DQS_DQSN_MODE | DIFFERENTIAL
AFI_DEBUG_INFO_WIDTH | 32
CALIBRATION_MODE | Full
NIOS_ROM_DATA_WIDTH | 32
NIOS_ROM_ADDRESS_WIDTH | 13
READ_FIFO_SIZE | 8
PHY_CSR_ENABLED | false
PHY_CSR_CONNECTION | INTERNAL_JTAG
USER_DEBUG_LEVEL | 1
TIMING_BOARD_DERATE_METHOD | AUTO
TIMING_BOARD_CK_CKN_SLEW_RATE | 2.0
TIMING_BOARD_AC_SLEW_RATE | 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE | 2.0
TIMING_BOARD_DQ_SLEW_RATE | 1.0
TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED | 2.0
TIMING_BOARD_AC_SLEW_RATE_APPLIED | 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED | 2.0
TIMING_BOARD_DQ_SLEW_RATE_APPLIED | 1.0
TIMING_BOARD_TIS | 0.0
TIMING_BOARD_TIH | 0.0
TIMING_BOARD_TDS | 0.0
TIMING_BOARD_TDH | 0.0
TIMING_BOARD_TIS_APPLIED | 0.375
TIMING_BOARD_TIH_APPLIED | 0.375
TIMING_BOARD_TDS_APPLIED | 0.25
TIMING_BOARD_TDH_APPLIED | 0.25
TIMING_BOARD_ISI_METHOD | AUTO
TIMING_BOARD_AC_EYE_REDUCTION_SU | 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H | 0.0
TIMING_BOARD_DQ_EYE_REDUCTION | 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME | 0.0
TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED | 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED | 0.0
TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED | 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED | 0.0
PACKAGE_DESKEW | false
AC_PACKAGE_DESKEW | false
TIMING_BOARD_MAX_CK_DELAY | 0.03
TIMING_BOARD_MAX_DQS_DELAY | 0.03
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN | 0.0
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED | 0.0
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX | 0.0
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED | 0.0
TIMING_BOARD_SKEW_BETWEEN_DIMMS | 0.05
TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED | 0.0
TIMING_BOARD_SKEW_WITHIN_DQS | 0.01
TIMING_BOARD_SKEW_BETWEEN_DQS | 0.08
TIMING_BOARD_DQ_TO_DQS_SKEW | 0.0
TIMING_BOARD_AC_SKEW | 0.03
TIMING_BOARD_AC_TO_CK_SKEW | 0.0
ENABLE_EXPORT_SEQ_DEBUG_BRIDGE | false
CORE_DEBUG_CONNECTION | EXPORT
ADD_EXTERNAL_SEQ_DEBUG_NIOS | false
ADD_EFFICIENCY_MONITOR | false
ENABLE_ABS_RAM_MEM_INIT | false
ENABLE_ABS_RAM_INTERNAL | false
ENABLE_ABSTRACT_RAM | false
ABS_RAM_MEM_INIT_FILENAME | meminit
DLL_DELAY_CTRL_WIDTH | 7
DLL_OFFSET_CTRL_WIDTH | 6
DELAY_BUFFER_MODE | HIGH
DELAY_CHAIN_LENGTH | 8
DLL_SHARING_MODE | None
NUM_DLL_SHARING_INTERFACES | 1
OCT_TERM_CONTROL_WIDTH | 16
OCT_SHARING_MODE | None
NUM_OCT_SHARING_INTERFACES | 1
AUTO_DEVICE | 5CSXFC6D6F31C8ES
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## nios2_qsys

altera_nios2_qsys v13.0

clk_50 | clk_reset | nios2_qsys
reset_n
pll_qsys | outclk0
clk
|  | data_master | onchip_memory2
|  | s1
|  | instruction_master
|  | s1
|  | data_master | jtag_uart
|  | avalon_jtag_slave
|  | d_irq
|  | irq
|  | data_master | timer
|  | s1
|  | d_irq
|  | irq
|  | data_master | sysid_qsys
|  | control_slave
|  | data_master | key
|  | s1
|  | d_irq
|  | irq
|  | data_master | ddr3_status
|  | s1
|  | jtag_debug_module_reset
|  | reset
|  | data_master | mem_if_ddr3_emif_fpga
|  | avl

## Parameters
setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_preciseSlaveAccessErrorException | false
setting_preciseIllegalMemAccessException | false
setting_preciseDivisionErrorException | false
setting_performanceCounter | false
setting_illegalMemAccessDetection | false
setting_illegalInstructionsTrap | false
setting_fullWaveformSignals | false
setting_extraExceptionInfo | false
setting_exportPCB | false
setting_debugSimGen | false
setting_clearXBitsLDNonBypass | true
setting_bit31BypassDCache | true
setting_bigEndian | false
setting_export_large_RAMs | false
setting_asic_enabled | false
setting_asic_synopsys_translate_on_off | false
setting_oci_export_jtag_signals | false
setting_bhtIndexPcOnly | false
setting_avalonDebugPortPresent | false
setting_alwaysEncrypt | true
setting_allowFullAddressRange | false
setting_activateTrace | true
setting_activateTestEndChecker | false
setting_activateMonitors | true
setting_activateModelChecker | false
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
muldiv_divider | false
mpu_useLimit | false
mpu_enabled | false
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
manuallyAssignCpuID | true
debug_triggerArming | true
debug_embeddedPLL | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
dcache_omitDataMaster | false
cpuReset | false
is_hardcopy_compatible | false
setting_shadowRegisterSets | 0
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mmu_TLBMissExcOffset | 0
debug_jtagInstanceID | 0
resetOffset | 0
exceptionOffset | 32
cpuID | 0
cpuID_stored | 0
breakOffset | 32
userDefinedSettings |
resetSlave | onchip_memory2.s1
mmu_TLBMissExcSlave |
exceptionSlave | onchip_memory2.s1
breakSlave | nios2_qsys.jtag_debug_module
setting_perfCounterWidth | 32
setting_interruptControllerType | Internal
setting_branchPredictionType | Automatic
setting_bhtPtrSz | 8
muldiv_multiplierType | EmbeddedMulFast
mpu_minInstRegionSize | 12
mpu_minDataRegionSize | 12
mmu_uitlbNumEntries | 4
mmu_udtlbNumEntries | 6
mmu_tlbPtrSz | 7
mmu_tlbNumWays | 16
mmu_processIDNumBits | 8
impl | Fast
icache_size | 4096
icache_tagramBlockType | Automatic
icache_ramBlockType | Automatic
icache_numTCIM | 0
icache_burstType | None
dcache_bursts | false
dcache_victim_buf_impl | ram
debug_level | Level1
debug_OCIOnchipTrace | _128
dcache_size | 2048
dcache_tagramBlockType | Automatic
dcache_ramBlockType | Automatic
dcache_numTCDM | 0
dcache_lineSize | 32
setting_exportvectors | false
setting_ecc_present | false
regfile_ramBlockType | Automatic
ocimem_ramBlockType | Automatic
mmu_ramBlockType | Automatic
bht_ramBlockType | Automatic
resetAbsoluteAddr | 1073872896
exceptionAbsoluteAddr | 1073872928
breakAbsoluteAddr | 1074006048
mmu_TLBMissExcAbsAddr | 0
dcache_bursts_derived | false
dcache_size_derived | 2048
dcache_lineSize_derived | 32
translate_on | "synthesis translate_on"
translate_off | "synthesis translate_off"
instAddrWidth | 31
dataAddrWidth | 31
tightlyCoupledDataMaster0AddrWidth | 1
tightlyCoupledDataMaster1AddrWidth | 1
tightlyCoupledDataMaster2AddrWidth | 1
tightlyCoupledDataMaster3AddrWidth | 1
tightlyCoupledInstructionMaster0AddrWidth | 1
tightlyCoupledInstructionMaster1AddrWidth | 1
tightlyCoupledInstructionMaster2AddrWidth | 1
tightlyCoupledInstructionMaster3AddrWidth | 1
instSlaveMapParam | <address-map><slave name='onchip_memory2.s1' start='0x40020000' end='0x4003F400' /><slave name='nios2_qsys.jtag_debug_module' start='0x40040800' end='0x40041000' /></address-map>
dataSlaveMapParam | <address-map><slave name='mem_if_ddr3_emif_fpga.avl' start='0x0' end='0x40000000' /><slave name='onchip_memory2.s1' start='0x40020000' end='0x4003F400' /><slave name='nios2_qsys.jtag_debug_module' start='0x40040800' end='0x40041000' /><slave name='timer.s1' start='0x40041000' end='0x40041020' /><slave name='ddr3_status.s1' start='0x40041020' end='0x40041030' /><slave name='key.s1' start='0x40041030' end='0x40041040' /><slave name='sysid_qsys.control_slave' start='0x40041040' end='0x40041048' /><slave name='jtag_uart.avalon_jtag_slave' start='0x40041048' end='0x40041050' /></address-map>
clockFrequency | 100000000
deviceFamilyName | CYCLONEV
internalIrqMaskSystemInfo | 7
customInstSlavesSystemInfo | <info/>
deviceFeaturesSystemInfo | ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
tightlyCoupledDataMaster0MapParam |
tightlyCoupledDataMaster1MapParam |
tightlyCoupledDataMaster2MapParam |
tightlyCoupledDataMaster3MapParam |
tightlyCoupledInstructionMaster0MapParam |
tightlyCoupledInstructionMaster1MapParam |
tightlyCoupledInstructionMaster2MapParam |
tightlyCoupledInstructionMaster3MapParam |
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
BIG_ENDIAN | 0
BREAK_ADDR | 0x40040820
CPU_FREQ | 100000000u
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x00000000
CPU_IMPLEMENTATION | "fast"
DATA_ADDR_WIDTH | 31
DCACHE_LINE_SIZE | 32
DCACHE_LINE_SIZE_LOG2 | 5
DCACHE_SIZE | 2048
EXCEPTION_ADDR | 0x40020020
FLUSHDA_SUPPORTED |
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 0
HAS_DEBUG_CORE | 1
HAS_DEBUG_STUB |
HAS_JMPI_INSTRUCTION |
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 4096
INITDA_SUPPORTED |
INST_ADDR_WIDTH | 31
NUM_OF_SHADOW_REG_SETS | 0
RESET_ADDR | 0x40020000

## onchip_memory2

altera_avalon_onchip_memory2 v13.0.1

clk_50 | clk_reset | onchip_memory2
reset1
nios2_qsys | data_master
s1
instruction_master
s1
pll_qsys | outclk0
clk1

## Parameters
allowInSystemMemoryContentEditor | false
blockType | AUTO
dataWidth | 32
dualPort | false
initMemContent | true
initializationFileName | onchip_memory2
instanceID | NONE
memorySize | 128000
readDuringWriteMode | DONT_CARE
simAllowMRAMContentsFile | false
simMemInitOnlyFilename | 0
singleClockOperation | false
slave1Latency | 1
slave2Latency | 1
useNonDefaultInitFile | false
useShallowMemBlocks | false
writable | true
autoInitializationFileName | DDR3_Qsys_onchip_memory2
deviceFamily | CYCLONEV
deviceFeatures | ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
derived_set_addr_width | 15
derived_gui_ram_block_type | Automatic
derived_is_hardcopy | false
derived_init_file_name | DDR3_Qsys_onchip_memory2
generateLegacySim | false

## Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
CONTENTS_INFO | ""
DUAL_PORT | 0
GUI_RAM_BLOCK_TYPE | AUTO
INIT_CONTENTS_FILE | DDR3_Qsys_onchip_memory2
INIT_MEM_CONTENT | 1
INSTANCE_ID | NONE
NON_DEFAULT_INIT_FILE_ENABLED | 0
RAM_BLOCK_TYPE | AUTO
READ_DURING_WRITE_MODE | DONT_CARE
SINGLE_CLOCK_OP | 0
SIZE_MULTIPLE | 1
SIZE_VALUE | 128000
WRITABLE | 1

## jtag_uart

altera_avalon_jtag_uart v13.0.1

clk_50 | clk_reset | jtag_uart
reset
nios2_qsys | data_master
avalon_jtag_slave
d_irq
irq
pll_qsys | outclk0
clk

## Parameters
allowMultipleConnections | false
hubInstanceID | 0
readBufferDepth | 64
readIRQThreshold | 8
simInputCharacterStream |
simInteractiveOptions | INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer | false
useRegistersForWriteBuffer | false
useRelativePathForSimFile | false
writeBufferDepth | 64
writeIRQThreshold | 8
avalonSpec | 2.0
legacySignalAllow | false
enableInteractiveInput | false
enableInteractiveOutput | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
READ_DEPTH | 64
READ_THRESHOLD | 8
WRITE_DEPTH | 64
WRITE_THRESHOLD | 8

## timer

altera_avalon_timer v13.0.1

clk_50 | clk_reset | timer
reset
nios2_qsys | data_master
s1
d_irq
irq
pll_qsys | outclk0
clk

## Parameters
alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 1
periodUnits | MSEC
resetOutput | false
snapshot | true
timeoutPulseOutput | false
systemFrequency | 100000000
timerPreset | FULL_FEATURED
periodUnitsString | ms
valueInSecond | 0
loadValue | 99999
mult | 0
ticksPerSec | 1000
slave_address_width | 3
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ALWAYS_RUN | 0
COUNTER_SIZE | 32
FIXED_PERIOD | 0
FREQ | 100000000
LOAD_VALUE | 99999
MULT | 0.001
PERIOD | 1
PERIOD_UNITS | ms
RESET_OUTPUT | 0
SNAPSHOT | 1
TICKS_PER_SEC | 1000.0
TIMEOUT_PULSE_OUTPUT | 0

## sysid_qsys

altera_avalon_sysid_qsys v13.0

clk_50 | clk_reset | sysid_qsys
reset
nios2_qsys | data_master
control_slave
pll_qsys | outclk0
clk

## Parameters
id | 0
timestamp | 1366324111
AUTO_CLK_CLOCK_RATE | 100000000
AUTO_DEVICE_FAMILY | CYCLONEV
deviceFamily | Cyclone V
generateLegacySim | false

## Software Assignments
ID | 0
TIMESTAMP | 1366324111

## pll_qsys

altera_pll v13.0

clk_50 | clk | pll_qsys
refclk
clk_reset
reset
|  | outclk0 | ddr3_status
|  | clk
|  | outclk0 | key
|  | clk
|  | outclk0 | sysid_qsys
|  | clk
|  | outclk0 | timer
|  | clk
|  | outclk0 | jtag_uart
|  | clk
|  | outclk0 | nios2_qsys
|  | clk
|  | outclk0 | onchip_memory2
|  | clk1

## Parameters
device_family | CYCLONEV
gui_device_speed_grade | 2
gui_pll_mode | Integer-N PLL
fractional_vco_multiplier | false
gui_reference_clock_frequency | 50.0
reference_clock_frequency | 50.0 MHz
gui_channel_spacing | 0.0
gui_operation_mode | normal
gui_feedback_clock | Global Clock
gui_fractional_cout | 32
pll_fractional_cout | 32
gui_dsm_out_sel | 1st_order
pll_dsm_out_sel | 1st_order
operation_mode | normal
gui_use_locked | true
gui_en_adv_params | false
gui_number_of_clocks | 1
number_of_clocks | 1
number_of_cascade_counters | 0
gui_multiply_factor | 1
gui_frac_multiply_factor | 1
gui_divide_factor_n | 1
gui_output_clock_frequency0 | 100.0
gui_divide_factor_c0 | 1
gui_actual_multiply_factor0 | 6
gui_actual_frac_multiply_factor0 | 1
gui_actual_divide_factor0 | 3
gui_actual_output_clock_frequency0 | 0 MHz
gui_ps_units0 | ps
gui_phase_shift0 | 0
gui_phase_shift_deg0 | 0
gui_actual_phase_shift0 | 0
gui_duty_cycle0 | 50
gui_output_clock_frequency1 | 100.0
gui_divide_factor_c1 | 1
gui_actual_multiply_factor1 | 1
gui_actual_frac_multiply_factor1 | 1
gui_actual_divide_factor1 | 1
gui_actual_output_clock_frequency1 | 0 MHz
gui_ps_units1 | ps
gui_phase_shift1 | 0
gui_phase_shift_deg1 | 0
gui_actual_phase_shift1 | 0
gui_duty_cycle1 | 50
gui_output_clock_frequency2 | 100.0
gui_divide_factor_c2 | 1
gui_actual_multiply_factor2 | 1
gui_actual_frac_multiply_factor2 | 1
gui_actual_divide_factor2 | 1
gui_actual_output_clock_frequency2 | 0 MHz
gui_ps_units2 | ps
gui_phase_shift2 | 0
gui_phase_shift_deg2 | 0
gui_actual_phase_shift2 | 0
gui_duty_cycle2 | 50
gui_output_clock_frequency3 | 100.0
gui_divide_factor_c3 | 1
gui_actual_multiply_factor3 | 1
gui_actual_frac_multiply_factor3 | 1
gui_actual_divide_factor3 | 1
gui_actual_output_clock_frequency3 | 0 MHz
gui_ps_units3 | ps
gui_phase_shift3 | 0
gui_phase_shift_deg3 | 0
gui_actual_phase_shift3 | 0
gui_duty_cycle3 | 50
gui_output_clock_frequency4 | 100.0
gui_divide_factor_c4 | 1
gui_actual_multiply_factor4 | 1
gui_actual_frac_multiply_factor4 | 1
gui_actual_divide_factor4 | 1
gui_actual_output_clock_frequency4 | 0 MHz
gui_ps_units4 | ps
gui_phase_shift4 | 0
gui_phase_shift_deg4 | 0
gui_actual_phase_shift4 | 0
gui_duty_cycle4 | 50
gui_output_clock_frequency5 | 100.0
gui_divide_factor_c5 | 1
gui_actual_multiply_factor5 | 1
gui_actual_frac_multiply_factor5 | 1
gui_actual_divide_factor5 | 1
gui_actual_output_clock_frequency5 | 0 MHz
gui_ps_units5 | ps
gui_phase_shift5 | 0
gui_phase_shift_deg5 | 0
gui_actual_phase_shift5 | 0
gui_duty_cycle5 | 50
gui_output_clock_frequency6 | 100.0
gui_divide_factor_c6 | 1
gui_actual_multiply_factor6 | 1
gui_actual_frac_multiply_factor6 | 1
gui_actual_divide_factor6 | 1
gui_actual_output_clock_frequency6 | 0 MHz
gui_ps_units6 | ps
gui_phase_shift6 | 0
gui_phase_shift_deg6 | 0
gui_actual_phase_shift6 | 0
gui_duty_cycle6 | 50
gui_output_clock_frequency7 | 100.0
gui_divide_factor_c7 | 1
gui_actual_multiply_factor7 | 1
gui_actual_frac_multiply_factor7 | 1
gui_actual_divide_factor7 | 1
gui_actual_output_clock_frequency7 | 0 MHz
gui_ps_units7 | ps
gui_phase_shift7 | 0
gui_phase_shift_deg7 | 0
gui_actual_phase_shift7 | 0
gui_duty_cycle7 | 50
gui_output_clock_frequency8 | 100.0
gui_divide_factor_c8 | 1
gui_actual_multiply_factor8 | 1
gui_actual_frac_multiply_factor8 | 1
gui_actual_divide_factor8 | 1
gui_actual_output_clock_frequency8 | 0 MHz
gui_ps_units8 | ps
gui_phase_shift8 | 0
gui_phase_shift_deg8 | 0
gui_actual_phase_shift8 | 0
gui_duty_cycle8 | 50
gui_output_clock_frequency9 | 100.0
gui_divide_factor_c9 | 1
gui_actual_multiply_factor9 | 1
gui_actual_frac_multiply_factor9 | 1
gui_actual_divide_factor9 | 1
gui_actual_output_clock_frequency9 | 0 MHz
gui_ps_units9 | ps
gui_phase_shift9 | 0
gui_phase_shift_deg9 | 0
gui_actual_phase_shift9 | 0
gui_duty_cycle9 | 50
gui_output_clock_frequency10 | 100.0
gui_divide_factor_c10 | 1
gui_actual_multiply_factor10 | 1
gui_actual_frac_multiply_factor10 | 1
gui_actual_divide_factor10 | 1
gui_actual_output_clock_frequency10 | 0 MHz
gui_ps_units10 | ps
gui_phase_shift10 | 0
gui_phase_shift_deg10 | 0
gui_actual_phase_shift10 | 0
gui_duty_cycle10 | 50
gui_output_clock_frequency11 | 100.0
gui_divide_factor_c11 | 1
gui_actual_multiply_factor11 | 1
gui_actual_frac_multiply_factor11 | 1
gui_actual_divide_factor11 | 1
gui_actual_output_clock_frequency11 | 0 MHz
gui_ps_units11 | ps
gui_phase_shift11 | 0
gui_phase_shift_deg11 | 0
gui_actual_phase_shift11 | 0
gui_duty_cycle11 | 50
gui_output_clock_frequency12 | 100.0
gui_divide_factor_c12 | 1
gui_actual_multiply_factor12 | 1
gui_actual_frac_multiply_factor12 | 1
gui_actual_divide_factor12 | 1
gui_actual_output_clock_frequency12 | 0 MHz
gui_ps_units12 | ps
gui_phase_shift12 | 0
gui_phase_shift_deg12 | 0
gui_actual_phase_shift12 | 0
gui_duty_cycle12 | 50
gui_output_clock_frequency13 | 100.0
gui_divide_factor_c13 | 1
gui_actual_multiply_factor13 | 1
gui_actual_frac_multiply_factor13 | 1
gui_actual_divide_factor13 | 1
gui_actual_output_clock_frequency13 | 0 MHz
gui_ps_units13 | ps
gui_phase_shift13 | 0
gui_phase_shift_deg13 | 0
gui_actual_phase_shift13 | 0
gui_duty_cycle13 | 50
gui_output_clock_frequency14 | 100.0
gui_divide_factor_c14 | 1
gui_actual_multiply_factor14 | 1
gui_actual_frac_multiply_factor14 | 1
gui_actual_divide_factor14 | 1
gui_actual_output_clock_frequency14 | 0 MHz
gui_ps_units14 | ps
gui_phase_shift14 | 0
gui_phase_shift_deg14 | 0
gui_actual_phase_shift14 | 0
gui_duty_cycle14 | 50
gui_output_clock_frequency15 | 100.0
gui_divide_factor_c15 | 1
gui_actual_multiply_factor15 | 1
gui_actual_frac_multiply_factor15 | 1
gui_actual_divide_factor15 | 1
gui_actual_output_clock_frequency15 | 0 MHz
gui_ps_units15 | ps
gui_phase_shift15 | 0
gui_phase_shift_deg15 | 0
gui_actual_phase_shift15 | 0
gui_duty_cycle15 | 50
gui_output_clock_frequency16 | 100.0
gui_divide_factor_c16 | 1
gui_actual_multiply_factor16 | 1
gui_actual_frac_multiply_factor16 | 1
gui_actual_divide_factor16 | 1
gui_actual_output_clock_frequency16 | 0 MHz
gui_ps_units16 | ps
gui_phase_shift16 | 0
gui_phase_shift_deg16 | 0
gui_actual_phase_shift16 | 0
gui_duty_cycle16 | 50
gui_output_clock_frequency17 | 100.0
gui_divide_factor_c17 | 1
gui_actual_multiply_factor17 | 1
gui_actual_frac_multiply_factor17 | 1
gui_actual_divide_factor17 | 1
gui_actual_output_clock_frequency17 | 0 MHz
gui_ps_units17 | ps
gui_phase_shift17 | 0
gui_phase_shift_deg17 | 0
gui_actual_phase_shift17 | 0
gui_duty_cycle17 | 50
output_clock_frequency0 | 100.0 MHz
phase_shift0 | 0 ps
duty_cycle0 | 50
output_clock_frequency1 | 0 MHz
phase_shift1 | 0 ps
duty_cycle1 | 50
output_clock_frequency2 | 0 MHz
phase_shift2 | 0 ps
duty_cycle2 | 50
output_clock_frequency3 | 0 MHz
phase_shift3 | 0 ps
duty_cycle3 | 50
output_clock_frequency4 | 0 MHz
phase_shift4 | 0 ps
duty_cycle4 | 50
output_clock_frequency5 | 0 MHz
phase_shift5 | 0 ps
duty_cycle5 | 50
output_clock_frequency6 | 0 MHz
phase_shift6 | 0 ps
duty_cycle6 | 50
output_clock_frequency7 | 0 MHz
phase_shift7 | 0 ps
duty_cycle7 | 50
output_clock_frequency8 | 0 MHz
phase_shift8 | 0 ps
duty_cycle8 | 50
output_clock_frequency9 | 0 MHz
phase_shift9 | 0 ps
duty_cycle9 | 50
output_clock_frequency10 | 0 MHz
phase_shift10 | 0 ps
duty_cycle10 | 50
output_clock_frequency11 | 0 MHz
phase_shift11 | 0 ps
duty_cycle11 | 50
output_clock_frequency12 | 0 MHz
phase_shift12 | 0 ps
duty_cycle12 | 50
output_clock_frequency13 | 0 MHz
phase_shift13 | 0 ps
duty_cycle13 | 50
output_clock_frequency14 | 0 MHz
phase_shift14 | 0 ps
duty_cycle14 | 50
output_clock_frequency15 | 0 MHz
phase_shift15 | 0 ps
duty_cycle15 | 50
output_clock_frequency16 | 0 MHz
phase_shift16 | 0 ps
duty_cycle16 | 50
output_clock_frequency17 | 0 MHz
phase_shift17 | 0 ps
duty_cycle17 | 50
gui_pll_auto_reset | Off
gui_pll_bandwidth_preset | Auto
gui_en_reconf | false
gui_en_dps_ports | false
gui_en_phout_ports | false
pll_type | General
pll_subtype | General
m_cnt_hi_div | 3
m_cnt_lo_div | 3
n_cnt_hi_div | 256
n_cnt_lo_div | 256
m_cnt_bypass_en | false
n_cnt_bypass_en | true
m_cnt_odd_div_duty_en | false
n_cnt_odd_div_duty_en | false
c_cnt_hi_div0 | 2
c_cnt_lo_div0 | 1
c_cnt_prst0 | 1
c_cnt_ph_mux_prst0 | 0
c_cnt_in_src0 | ph_mux_clk
c_cnt_bypass_en0 | false
c_cnt_odd_div_duty_en0 | true
c_cnt_hi_div1 | 1
c_cnt_lo_div1 | 1
c_cnt_prst1 | 1
c_cnt_ph_mux_prst1 | 0
c_cnt_in_src1 | ph_mux_clk
c_cnt_bypass_en1 | true
c_cnt_odd_div_duty_en1 | false
c_cnt_hi_div2 | 1
c_cnt_lo_div2 | 1
c_cnt_prst2 | 1
c_cnt_ph_mux_prst2 | 0
c_cnt_in_src2 | ph_mux_clk
c_cnt_bypass_en2 | true
c_cnt_odd_div_duty_en2 | false
c_cnt_hi_div3 | 1
c_cnt_lo_div3 | 1
c_cnt_prst3 | 1
c_cnt_ph_mux_prst3 | 0
c_cnt_in_src3 | ph_mux_clk
c_cnt_bypass_en3 | true
c_cnt_odd_div_duty_en3 | false
c_cnt_hi_div4 | 1
c_cnt_lo_div4 | 1
c_cnt_prst4 | 1
c_cnt_ph_mux_prst4 | 0
c_cnt_in_src4 | ph_mux_clk
c_cnt_bypass_en4 | true
c_cnt_odd_div_duty_en4 | false
c_cnt_hi_div5 | 1
c_cnt_lo_div5 | 1
c_cnt_prst5 | 1
c_cnt_ph_mux_prst5 | 0
c_cnt_in_src5 | ph_mux_clk
c_cnt_bypass_en5 | true
c_cnt_odd_div_duty_en5 | false
c_cnt_hi_div6 | 1
c_cnt_lo_div6 | 1
c_cnt_prst6 | 1
c_cnt_ph_mux_prst6 | 0
c_cnt_in_src6 | ph_mux_clk
c_cnt_bypass_en6 | true
c_cnt_odd_div_duty_en6 | false
c_cnt_hi_div7 | 1
c_cnt_lo_div7 | 1
c_cnt_prst7 | 1
c_cnt_ph_mux_prst7 | 0
c_cnt_in_src7 | ph_mux_clk
c_cnt_bypass_en7 | true
c_cnt_odd_div_duty_en7 | false
c_cnt_hi_div8 | 1
c_cnt_lo_div8 | 1
c_cnt_prst8 | 1
c_cnt_ph_mux_prst8 | 0
c_cnt_in_src8 | ph_mux_clk
c_cnt_bypass_en8 | true
c_cnt_odd_div_duty_en8 | false
c_cnt_hi_div9 | 1
c_cnt_lo_div9 | 1
c_cnt_prst9 | 1
c_cnt_ph_mux_prst9 | 0
c_cnt_in_src9 | ph_mux_clk
c_cnt_bypass_en9 | true
c_cnt_odd_div_duty_en9 | false
c_cnt_hi_div10 | 1
c_cnt_lo_div10 | 1
c_cnt_prst10 | 1
c_cnt_ph_mux_prst10 | 0
c_cnt_in_src10 | ph_mux_clk
c_cnt_bypass_en10 | true
c_cnt_odd_div_duty_en10 | false
c_cnt_hi_div11 | 1
c_cnt_lo_div11 | 1
c_cnt_prst11 | 1
c_cnt_ph_mux_prst11 | 0
c_cnt_in_src11 | ph_mux_clk
c_cnt_bypass_en11 | true
c_cnt_odd_div_duty_en11 | false
c_cnt_hi_div12 | 1
c_cnt_lo_div12 | 1
c_cnt_prst12 | 1
c_cnt_ph_mux_prst12 | 0
c_cnt_in_src12 | ph_mux_clk
c_cnt_bypass_en12 | true
c_cnt_odd_div_duty_en12 | false
c_cnt_hi_div13 | 1
c_cnt_lo_div13 | 1
c_cnt_prst13 | 1
c_cnt_ph_mux_prst13 | 0
c_cnt_in_src13 | ph_mux_clk
c_cnt_bypass_en13 | true
c_cnt_odd_div_duty_en13 | false
c_cnt_hi_div14 | 1
c_cnt_lo_div14 | 1
c_cnt_prst14 | 1
c_cnt_ph_mux_prst14 | 0
c_cnt_in_src14 | ph_mux_clk
c_cnt_bypass_en14 | true
c_cnt_odd_div_duty_en14 | false
c_cnt_hi_div15 | 1
c_cnt_lo_div15 | 1
c_cnt_prst15 | 1
c_cnt_ph_mux_prst15 | 0
c_cnt_in_src15 | ph_mux_clk
c_cnt_bypass_en15 | true
c_cnt_odd_div_duty_en15 | false
c_cnt_hi_div16 | 1
c_cnt_lo_div16 | 1
c_cnt_prst16 | 1
c_cnt_ph_mux_prst16 | 0
c_cnt_in_src16 | ph_mux_clk
c_cnt_bypass_en16 | true
c_cnt_odd_div_duty_en16 | false
c_cnt_hi_div17 | 1
c_cnt_lo_div17 | 1
c_cnt_prst17 | 1
c_cnt_ph_mux_prst17 | 0
c_cnt_in_src17 | ph_mux_clk
c_cnt_bypass_en17 | true
c_cnt_odd_div_duty_en17 | false
pll_vco_div | 2
pll_cp_current | 30
pll_bwctrl | 2000
pll_output_clk_frequency | 300.0 MHz
pll_fractional_division | 1
mimic_fbclk_type | gclk
pll_fbclk_mux_1 | glb
pll_fbclk_mux_2 | fb_1
pll_m_cnt_in_src | ph_mux_clk
gui_parameter_list | M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX
gui_parameter_values | 3,3,256,256,false,true,false,false,2,1,1,0,ph_mux_clk,false,true,2,30,2000,300.0 MHz,1,gclk,glb,fb_1,ph_mux_clk
gui_mif_generate | false
gui_enable_mif_dps | false
gui_dps_cntr | C0
gui_dps_num | 1
gui_dps_dir | Positive
gui_refclk_switch | false
gui_refclk1_frequency | 100.0
gui_switchover_mode | Automatic Switchover
gui_switchover_delay | 0
gui_active_clk | false
gui_clk_bad | false
refclk1_frequency | 100.0 MHz
pll_clk_loss_sw_en | false
pll_manu_clk_sw_en | false
pll_auto_clk_sw_en | false
pll_clkin_1_src | clk_0
pll_clk_sw_dly | 0
gui_enable_cascade_out | false
gui_enable_cascade_in | false
pll_clkin_0_src | clk_0
gui_pll_cascading_mode | Create an adjpllin signal to connect with an upstream PLL
AUTO_REFCLK_CLOCK_RATE | 50000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## key

altera_avalon_pio v13.0.1

clk_50 | clk_reset | key
reset
nios2_qsys | data_master
s1
d_irq
irq
pll_qsys | outclk0
clk

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | true
direction | Input
edgeType | RISING
generateIRQ | true
irqType | EDGE
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 4
clockRate | 100000000
derived_has_tri | false
derived_has_out | false
derived_has_in | true
derived_do_test_bench_wiring | false
derived_capture | true
derived_edge_type | RISING
derived_irq_type | EDGE
derived_has_irq | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 1
DATA_WIDTH | 4
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | RISING
FREQ | 100000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | EDGE
RESET_VALUE | 0

## ddr3_status

altera_avalon_pio v13.0.1

nios2_qsys | data_master | ddr3_status
s1
jtag_debug_module_reset
reset
clk_50 | clk_reset
reset
pll_qsys | outclk0
clk

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 3
clockRate | 100000000
derived_has_tri | false
derived_has_out | false
derived_has_in | true
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 3
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 100000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

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