Nios DDR3 Test Example Project TimeQuest Negative Setup Slack

Hello everyone,

I've been trying to understand the workings of the timing analyser recently. I need to implement an SDRAM Controller with Uniphy in my design.

So I opened up an example project called "SoCKit_DDR3_Nios_Test. I noticed it is very similar to mine, it has a nios processor, onchip mem, clock, and so on.

After compiling and constraining the I received a setup violation error. I don't know what is wrong with my constraint. I doubt I need to use set_input_delay or set_output_delay, since the sdc file doesn't even have clock groupings, which I added later on to try to repair the setup slack. The clock groupings managed to correct the negative slack on the generated clock "u0|pll_qsys|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk"

This is my sdc file.

create_clock -period 20 
create_clock -period 20 
create_clock -period 20 
create_clock -period 20 
derive_pll_clocks
derive_clock_uncertainty
set_clock_groups -asynchronous -group {OSC_50_B3B 
                                                    OSC_50_B4A 
                                                    OSC_50_B5B 
                                                    OSC_50_B8A 
                                        } 
                                        -group { 
                                                    u0|pll_qsys|altera_pll_i|general.gpll~FRACTIONAL_PLL|vcoph 
                                                    u0|pll_qsys|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk 
                                        } 
                                        -group { 
                                                    u0|mem_if_ddr3_emif_fpga|DDR3_Qsys_mem_if_ddr3_emif_fpga_p0_sampling_clock 
                                        } 
                                        -group { 
                                                    u0|mem_if_ddr3_emif_fpga|pll0|pll_addr_cmd_clk 
                                                    u0|mem_if_ddr3_emif_fpga|pll0|pll_avl_clk 
                                                    u0|mem_if_ddr3_emif_fpga|pll0|pll_dq_write_clk 
                                                    u0|mem_if_ddr3_emif_fpga|pll0|pll_write_clk 
                                        } 
                                        -group { 
                                                        u0|mem_if_ddr3_emif_fpga|pll0|pll_afi_clk 
                                        } 
                                        -group { 
                                                    DDR3_CK_n 
                                                    DDR3_CK_p 
                                                    DDR3_DQS_n_OUT 
                                                    DDR3_DQS_n_OUT 
                                                    DDR3_DQS_n_OUT 
                                                    DDR3_DQS_n_OUT 
                                                    DDR3_DQS_p_IN 
                                                    DDR3_DQS_p_OUT 
                                                    DDR3_DQS_p_IN 
                                                    DDR3_DQS_p_OUT 
                                                    DDR3_DQS_p_IN 
                                                    DDR3_DQS_p_OUT 
                                                    DDR3_DQS_p_IN 
                                                    DDR3_DQS_p_OUT 
                                        } 

I can't really wrap my head around the behind-the-scene workings of Altera. Can someone please explain me?

I look forward to any replies :)

BTW I'm using Quartus 14.1