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osi-hw's avatar
osi-hw
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3 years ago
Solved

Nios boot (Passive serial Configuration)

Hi, I am using a max 10 (CPLD) to configure a cyclone V (passive serial configuration). The FPGA image is stored in. an external parallel flash connected to the CPLD. I want to know how to us...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

MAX10 only supports internal configuration (from built in FLASH) and JTAG.

See: https://www.intel.com/content/www/us/en/programmable/documentation/sss1393988509894.html

However you can use the PFL IP core in Intel MAX® devices (Intel MAX 10, MAX II, and MAX V devices) or all other FPGAs to program flash memory devices efficiently through the JTAG interface and to control configuration from the flash memory device to the Intel FPGA.

See: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf

May check out this handbook https://www.intel.com/content/www/us/en/docs/programmable/683689/current/introduction-28202.html page 332 onwards.

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

  • osi-hw's avatar
    osi-hw
    Icon for New Contributor rankNew Contributor
    3 years ago
    Hi,
    Thank you for your reply.
    The nios I want to boot is in the cyclone V not mac 10.

    the architecture is like this



    Parallel Flash -> CPLD -> (passive serial) Cyclone V (with Nios)

    To boot the nios in DDR3 using this configuration, the parallel flash should be connected to cyclone V too ? and then follow the steps in the document you sent me ?
    Best regards,