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New ContributorNios boot (Passive serial Configuration)
Hi,
Click Auto Detect after the programming successful. Click Yes if you are asked to overwrite existing settings. The CFI flash device will be detected and attached to the MAX CPLD.
You may refer to the steps in these documents and designs:
https://www.intel.com/content/www/us/en/docs/programmable/683689/current/introduction-28202.html (Page 332)
https://www.intel.com/content/www/us/en/design-example/714910/cyclone-v-nios-ii-processor-booting-from-cfi-flash.html (Design Store)
**The boot-copier design in documents use the inbuilt MAX V cpld.
Best Regards,
Sheng
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.
Super ContributorHi,
MAX10 only supports internal configuration (from built in FLASH) and JTAG.
See: https://www.intel.com/content/www/us/en/programmable/documentation/sss1393988509894.html
However you can use the PFL IP core in Intel MAX® devices (Intel MAX 10, MAX II, and MAX V devices) or all other FPGAs to program flash memory devices efficiently through the JTAG interface and to control configuration from the flash memory device to the Intel FPGA.
See: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
May check out this handbook https://www.intel.com/content/www/us/en/docs/programmable/683689/current/introduction-28202.html page 332 onwards.
Best Regards,
Sheng
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.
osi-hwHi,
Thank you for your reply.
The nios I want to boot is in the cyclone V not mac 10.
the architecture is like this
Parallel Flash -> CPLD -> (passive serial) Cyclone V (with Nios)
To boot the nios in DDR3 using this configuration, the parallel flash should be connected to cyclone V too ? and then follow the steps in the document you sent me ?
Best regards,
