Nintendo DS Passthrough

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i'm not a Verilog guy but it doesn't look like you register card logic which could cause problems like this. how fast does the DS data run?

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What do you mean with I don't register card logic?

The DS clock runs at approx 6.7 MHz.

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you specify

inout [7:0] DSCARD0_DAT;

as an 8 bit bidir signal

you correctly used assignments for that, but only for 6 bit [5:0] and no assignment for bit 6 and 7

so you can combine these lines as

assign DSCARD0_DAT[7:0] = (DSCARD0_RES & ~DSCARD0_RCS & ~IsCommand ) ? DSCARD1_DAT[7:0] : 8'bzzzzzzzz;

assign DSCARD1_DAT[7:0] = (DSCARD0_RES & ~DSCARD0_RCS & IsCommand ) ? DSCARD0_DAT[7:0] : 8'bzzzzzzzz;

your problem no starts here where you try to switch the direction from card0 to card1 and vice versa with a registered signal. this is some kind of an asynchron dataloop, hard to dig down the problem.

i have no information about how hard the timing must be in this application but if possible try to write a fully synchronus design and pipe some of the signals that the or clock synchron to each other.

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Yeah the reason for the seperate DSCARDx_DAT[] lines is that I was testing the signals one-by-one, while leaving 6 and 7 directly connected between CARD0 and CARD1.

What do you mean the problem is with the registered signal? Could you explain this some more?

How would a fully synchronous design look like?

Thanks in advance