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Altera_Forum
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13 years ago

Newbie Verilog Q regarding Memory Accesses

Have developed a module with a memory element as follows: reg page_0_statement [65535:0]; I am attempting to access the memory from a NIOS C application as a 32 bit unsigned int. Therefore...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I'm not familiar with Verilog, but how did you define page_0_statement?

You should be able to define it as an array of 32-bit vectors and then directly use the address from the Avalon MM slave as index without adding padding 0s.

It can be a good idea to use Signaltap probes on your component to see what's happening when your software accesses the component.