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Altera_Forum's avatar
Altera_Forum
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17 years ago

Newbie can't load data into fifo

I am new to FPGAs. I'm unable to clock data into the mega function FIFOs (both lpm_fifo_dc and dcfifo) in the simulator. I assume I'm doing something wrong, so I've retraced my steps for creating a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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rdusedw is registered and synchronous with rdclk

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Ok I didn't realize this. I changed the simulation to clock rdclk and now I see that rdusedw and rdempty display the correct values. Thanks a bunch.