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Altera_Forum's avatar
Altera_Forum
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16 years ago

Newbie can't load data into fifo

I am new to FPGAs. I'm unable to clock data into the mega function FIFOs (both lpm_fifo_dc and dcfifo) in the simulator. I assume I'm doing something wrong, so I've retraced my steps for creating a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi Jake,

I'm only trying to make the point that I cannot load data into the fifo. I intentionally do not clock rdclk, so I'm expecting that the fifo should fill up (rdusedw[] should not remain at 0x00).