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Altera_Forum's avatar
Altera_Forum
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17 years ago

Newbie can't load data into fifo

I am new to FPGAs. I'm unable to clock data into the mega function FIFOs (both lpm_fifo_dc and dcfifo) in the simulator. I assume I'm doing something wrong, so I've retraced my steps for creating a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You can't force rdclk low. Do you want the complicated explanation of how Dual-clock FIFO's work or do you want to take my word for it?

Jake