New bie on timing constraints

Actually, I talked about multiple related clocks, but I forgot about the more applicable one, which again is for I/O constraints. For example, if you have an oscillator driving an external device and the FPGA, and it takes 1ns to get to the external device and 2ns to get to the FPGA, then you can add latency of 1ns to the virtual clock and 2ns to the FPGA clock. Now your clock delay/skew will be modeled in your I/O timing. If the external device has a Tco of 8ns and minTco of 4ns, you can just do a set_input_delay -max 8 and another set_input_delay -min 4. (Most users rolls the clock skew into this delay, which would make the -max value 7 and -min 3, but set_clock_latency will do this for you).