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Altera_Forum
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13 years ago

New bie on timing constraints

Hello Experts, I have been new in Altera & Quartus. I am trying to understand the need for constraints like 'set_clock_latency' , 'set_clock_uncertainity' in FPGA's. For me these constr...
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Altera_Forum
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13 years ago

In summary, most of the time, yes.

But if your design has multiple related clocks coming into the FPGA, you'll probably need to use use set_clock_latency to model that.

If you have a high jitter clock and can't afford to use a PLL to filter it, you should also use it.

Those are rare situations; but it's best to know they exist.