New bie on timing constraints

Yes, we need this kind of modeling. Even though the PLLs filter jitter, their output is not totally jitter free.

If you take a look at TQ's timing reports, you'll notice that "derive_clock_uncertainty" adds uncertainty to all clocks.

But we don't have to do this modeling ourselves, most of the time.

We usually can safely assume jitter in the input clocks is zero and let derive_clock_uncertainty do the work for us.

I know I rarely do.