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Thanks for sharing your thoughts.
@Kaz,
I was just curious to understand, how setting 'clock_latency/uncertainity' would be helpful is setting false/mcp's. I could not make out the relation. Can you please elaborate on this point.
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I misunderstood your specific question. There is no relation of false path/MCP to clock delay or uncertainty. I just wanted to point out that these should be possible candidates for automation in near future!
clock jitter can be entered if you know your figure. This will in effect lower the clock period.
clock delay is something I never use.
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Also, what is dsp builder. I assume this is something to do with DSP core generator.
Here, again shall we live by giving input delays since there is not CTS like ASIC in FPGA.
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Yes DSPBuilder is Altera's tool to generate rtl for various dsp functions and it has strict rule to enter exact clock speed so you can't add a bit of edge to improve fmax should it not meet timing.
In normal work I may want to increase clock jitter to get better fmax for a given clock speed or I may equally do that by adding a bit of edge to the actual clock speed. The latter can't be used with dspbuilder.
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