New bie on timing constraints

Thanks for sharing your thoughts.

@Kaz,

I was just curious to understand, how setting 'clock_latency/uncertainity' would be helpful is setting false/mcp's. I could not make out the relation. Can you please elaborate on this point.

Also, what is dsp builder. I assume this is something to do with DSP core generator.

Here, again shall we live by giving input delays since there is not CTS like ASIC in FPGA.

@rbugalho,

My understanding is, even if FPGA has one or more clock inputs, the DCM output will be stable and jitter free. I suppose that is how PLL primitives are mad for.

In that case, do we need this kind of modelling.

Have you guys seen this anytimes using this constraints if the chip top level or clock coming from ALTPLL, DCM/PLL etc.

Regards,

frk