New bie on timing constraints

Very rare to need them. But useful to have when needed.

set_clock_uncertainty:

- add a "just in case" safety margin

- add a safety margin to account for jitter in the input clock

set_clock_uncertainty or set_clock_latency (the latter is more appropriate here):

- model external delay variance, when the FPGA has two or more related clock inputs.

On ASICs, the most common use of set_clock_uncertainty is actually to add a margin for clock skew during synthesis and place, as the clock tree is not yet built and the real skew is unknown.