New bie on timing constraints

derive_clock_uncertainty calls out set_clock_uncertainty for each transfer, so you don't need to do this yourself. (And derive_clock_uncertainty gets called automatically). You could use it to model jitter on an external(virtual) clock, but I never seen that done.

I've seen set_clock_latency used to model external clock delays. For example, if two clocks are coming in that are related, you could have different latency on the two clocks and their relationships inside the FPGA will now be altered. Very seldom needed, and when I've seen it, most users just modify the clock waveform to get similar results.

In the end, most designs never use these. My 2 cents, but I'll be curious what others say...