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Honored Contributor
Honored ContributorNegative spykes on all internal signals in EP4CE15E22C7N
Hello. I use the EP4CE15E22C7N device. (E144 package). The only clock connected is 50MHz, 3.3V to one of the clk inputs. The VCCIO connected to clean 3.3VDC, the VCCINT and VCCPLL to clean 1.2...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I just found something strange in the HDL evaluation board at page 6 http://www.hdl.co.jp/en/spc/acm/acm-...man-en-v10.pdf they write that the JTAG-P2 is connected to 3.3V (the VCCIO), but ALTERA, in their manual write that it should be 2.5V... --- Quote End --- A JTAG voltage of 2.5V is suggested to reduce the absolute voltage level of possible overshoots at the FPGA pins. Nevertheless, all recent FPGA families can still work with 3.3V JTAG supply. The point can't explain your observations, I think. As far as I understood, all results have been obtained through SignalTap. Did you ever feed a generated signal to an output pin and checked it with an oscilloscope? Did you verify, that the clock frequency is actually 50 MHz? Is the design operated from the input clock or a PLL? In the latter case, did you check, if the PLL is permanently locked by sending the locked signal to a pin? Are you sure, that your design state doesn't possibly depend on floating FPGA inputs? P.S.: Assuming, there may be an issue with JTAG or SignalTap operation, you should perform the hardware check with and without SignalTap activities.
