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Honored Contributor
Honored ContributorNegative spykes on all internal signals in EP4CE15E22C7N
Hello. I use the EP4CE15E22C7N device. (E144 package). The only clock connected is 50MHz, 3.3V to one of the clk inputs. The VCCIO connected to clean 3.3VDC, the VCCINT and VCCPLL to clean 1.2...
Altera_ForumHonored Contributor
Honored Contributorits really very simple board. The FPGA just connected to serial FLASH for future + JTAG for debug. It has single 50MHz external oscillator.
The other IO's are are for management of analog ADCs, DACs AMUXes I got the same behavior on 3 different boards. I just found something strange in the HDL evaluation board at page 6 http://www.hdl.co.jp/en/spc/acm/acm-023/acm023r1-man-en-v10.pdf they write that the JTAG-P2 is connected to 3.3V (the VCCIO), but ALTERA, in their manual write that it should be 2.5V... I begin to think that maybe, nevertheless the problem is in the JTAG interface despite of that i had checked this.... Tomorrow i'll get the boards again and re-check this issue again...
