Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Need some help to use altdq and altdqs megafunction.

Hi, I am working on memory controller. In that data received from memory is edge aligned with clock. I want to give phase shift of incoming clock to 90 degree so that I can receive data cent...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

As TEntner learned us, Cyclone IV devices don't have a DLL in the DQS block.

The ONFI spec allows a 3 to 20 nsec delay for sending DQS back on read, which means you cannot relate the incoming DQS to any clock in the FPGA, in other words: it seems you have to use either CycloneII, StratixII , StratixIII ...

At what speed do you want / need to run the Flash memory?