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Altera_Forum
Honored Contributor
Honored ContributorNeed salvation~~
Hi, all: I'm really frustrated today. After a long period effort, it seems I made little progress. Problems always occur when you think you're ready, and sometimes the problem turns out t...
Altera_ForumHonored Contributor
Honored ContributorHi, BadOmen:
Thank you very much for the advice. Our project is rather simple: we capture 6 channels data simutaneouly using FPGA, do a little processing inside FPGA, then reshape the format of the data and send them out to DSP. What I found frustrating is the mismatch of PCB design and software (here I mean verilog coding, not higer level language); these two parts of work are done by two men. Since the PCB is already, some effort must be taken by coding and change of structure which is painful. Absence of the "achitect engineer" have some effect on the current situation. However, next time I'd rather do the software first.
