need help with some vhdl syntax

std_logic' and std_logic_vector' is not a type conversion, it is a type qualification.

If I have the following literal: "110100101", it could be a string, it could be a std_logic_vector, it could be a bit_vector etc. Similarly, '0' and '1' could a character or a std_logic value. This can be a problem, especially with functions with multiple definitions that take different types. The most common one is the write procedure from textio.

If I have the following line:

write(my_line, "110101");

The compile has no idea if Im trying to write a string or a bit_vector, and will throw an error. To fix it you write:

write(my_line, string'("110101"));

and this tells the compiler that it is a string you meant, rather than a bit_vector.

if you leave the ' out, it is a type conversion.