Altera_Forum
Honored Contributor
Honored ContributorNeed help with parity checker!
Hi guys i'm totally new to VHDL and this is the start of my 2nd week learning it and i'm supposed to design a test and test bench on 8-bit parity checker (D0 to D7 as inputs) with 2 outputs (ouput_even and output_odd). When the sum of '1/HIGH's through D1-D7 is even, the output_even would show a HIGH while the output_odd would give a LOW. Likewise, when the sum of 1/HIGH's through D1-D7 is odd, output_even would show a LOW while output_odd would give a HIGH. Any takers? Please help! :confused:
