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Altera_Forum
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14 years ago

Need help with parity checker!

Hi guys i'm totally new to VHDL and this is the start of my 2nd week learning it and i'm supposed to design a test and test bench on 8-bit parity checker (D0 to D7 as inputs) with 2 outputs (ouput_e...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

odd <= ((D0 xor D1) xor (D2 xor D3)) xor ((D4 xor D5) xor (D6 xor D7));

even <= not odd;