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alperenpalp's avatar
alperenpalp
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5 years ago

Need Help with FIR II TDM.

Hello,

I've been trying to get FIR filter working for quite a while, but I've been runnig into problems.

I am basically trying to implement 51 tap low-pass filter. I am also trying to save hardware resources by trying to implement TDM. That's basically when I start to have problems.

Here are some specs

no interpolation or decimation.

Number of channels: 1

Input Sampling Rate: 15 MSPS

Clock Rate: 60 MHz

input width: 16 bits

output width: 38 bits.

First of all, when I try to test this source_valid signals is asserted at 7.5 MSPS not 15 MSPS. ( source_valid is asserted every eighth cycle instead of 4)

In FIR II IP user guide and page 33 it talks about TDM to save hardware resources. It also talks about serializer and deserializer at the input and output, respectively. I don't understand what kind of serialization I should implement. Can anyone tell me how to handle input data and interpret output data correctly?

I attach the IP that I built and modelsim project that I use to verify my design.

FIR IP: unsaved.qsys

Modelsim project: synthesis/FIR_filter_test.mpf

Please check the files.

Thanks in advance.

13 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    As I understand it, you have some inquiries related to the FIR serializer and deserializer for the TDM. Allow me to try explaining. Take an example of TDM = 2 + clock rate = 30MHz. Assuming there are two input streams with sample rate = 15MSPS, the serializer will convert the take 1 sample from each input stream in parallel and then serialize into one stream at 30MSPS. After the FIR, the deserializer will separate the streams.


    Please let me know if there is any concern. Thank you.


    • alperenpalp's avatar
      alperenpalp
      Icon for New Contributor rankNew Contributor
      5 years ago

      I know we had this discussion before, but I am still no convinced about this issue.

      I can clearly see that the IP is expecting only one channel as this is obvious from Info Message in platform designer (see attached pic, Soru). I also set the max num of channels to 1 in filter specifications settings.

      I would really like you to review your suggestion about that. The IP clearly does not expect more than on inpur stream. There is clearly a setting for that in the filter specification tab named "max number of channels" , it is set to 1 not 2 or 3, and it's also indicated in the info message that the IP is expecting only one channel, not more.

      Can you please review your response or confirm with someone else?

      Thank you for your patience.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Thanks for your update. I will further look into this and discuss with peers. For your information, I am currently out of office and will be back early next week. I will try to provide you an update on progress by end of next week. Please ping me if you do not hear back from me. Thank you.


  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Sorry for the delay. Sorry if there is any confusion with my previous explanation. I am not referring to 2 channels but just trying to explain using serialization of two streams into one. Let me try to explain in a different way using the following example:


    Assuming the input sample rate = 50MSPS. By default the required clock rate = 50MHz. However, in order to reduce the number of multipliers used, we use TDM = 2 as example to halve the multipliers. With TDM = 2, the required clock rate to the FIR IP is doubled = 100MHz.


    This reduces the number of multipliers by 2x but increases logic utilization to implement the Serializer and Deserializer. At the top level, the operation of the serializer and deserializer are transparent to the user. What user need to do, is to supply 2x clock rate than the sample rate or the frequency and sample rate that you configure in IP.


    Back to your configuration case, you have input sample rate = 15MSPS and clock rate = 60MHz. In other words, you are configuring the IP to implement TDM = 4. The number of multipliers utilized should reduced by 4x. During your test, you should supply input with sample rate of 15MSPS but not the 7.5MSPS because the IP is expecting 15MSPS. With 15MSPS, you would get 15MSPS at output as well. If you would like to supply 7.5MSPS, you should configure the same in the IP configuration.


    Please let me know if there is any concern. Thank you.


    • alperenpalp's avatar
      alperenpalp
      Icon for New Contributor rankNew Contributor
      5 years ago

      Thank you for your response,

      I feed 15MSPS input to the IP, but I get 7.5MSPS output which is half of the input rate. Please look at the attached picture.

      You can see that the clock is 60 MHZ and the source_valid is asserted at a rate of 7.5MHz(period is about 133 ns which is 7.5 MHz). What am I doing wrong? Clock rate is set to 60MHz and the input sampling rate is set to 15MSPS.

      I am just trying to validate the impulse response of the filter and it's all over the place it seems like the IP skipping almost all of the coefficients.

      Can you try to implement similar to see if you get a similar result

      Thanks!

      • alperenpalp's avatar
        alperenpalp
        Icon for New Contributor rankNew Contributor
        5 years ago

        Sorry I forgot to to attach the picture.

        Here are the results as you can see the output 2 times lower than the input rate 7.5MSPS and the impulse response is all over the place.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Sorry for confusion. Just would like to check with you what is your clock rate and input sample rate? From the screenshot, seems like the sink_valid is held at constant 1. This would imply input sample rate = clock rate. Please let me know if there is any concern. Thank you.


    • alperenpalp's avatar
      alperenpalp
      Icon for New Contributor rankNew Contributor
      5 years ago

      Clock rate is 60 MHz and the input rate 15 MSPS.

      Should I toggle the sink_valid signal at input sample rate?

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Yes, you should toggle the sink_valid per your sample rate. If not, for every clock cycle, it will sample the data like oversampling.


    Thank you.


  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.