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alperenpalp's avatar
alperenpalp
Icon for New Contributor rankNew Contributor
5 years ago

Need Help with FIR II TDM.

Hello, I've been trying to get FIR filter working for quite a while, but I've been runnig into problems. I am basically trying to implement 51 tap low-pass filter. I am also trying to save hardwa...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Sorry for confusion. Just would like to check with you what is your clock rate and input sample rate? From the screenshot, seems like the sink_valid is held at constant 1. This would imply input sample rate = clock rate. Please let me know if there is any concern. Thank you.


  • alperenpalp's avatar
    alperenpalp
    Icon for New Contributor rankNew Contributor
    5 years ago

    Clock rate is 60 MHz and the input rate 15 MSPS.

    Should I toggle the sink_valid signal at input sample rate?