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Honored Contributor
Honored ContributorNeed help with external SRAM read/write
Hi, I am a newbie to the FPGA. Currently, I am trying to redesign a FPGA to include the FFT. The FPGA chip used is Cyclone II family EP2C8F256I8. The microprocessor used is a ARM9 LPC3180. The ...
Altera_ForumHonored Contributor
Honored ContributorTypically such FIFOs as you mention on the Arm are used to allow efficient programming and increase the transfer rate on the SPI line.
So no primary influence for your implementation if it should "just work". It might get of interest when speed is topic. It depends a little on how you readout the data using the SPI bus. The question you have to ask is: When the FPGA gets the command to respond with SRAM data, how much time (clock cycles on FPGA, clock cycles on SPI bus) is needed until the bits are available in a register in the FPGA. If it is fast enough, it could be possible to respond in time. If not you could introduce a data delay of e.g. one SRAM value by setting the first response to e.g. always 0x0, and then the data. So to sum up: It depends on timing (clocks involved) and the protocol you use on the SPI bus.
