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Altera_Forum's avatar
Altera_Forum
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15 years ago

Need help from Guru

Hey guys, I am looking for some help in the syntax. Following is my syntax to perform a voting system. Library IEEE; USE IEEE.std_logic_1164.all; Entity Gproject IS PORT ( Se0, S...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Your are assigning X(3) twice:

- X(3) <= '0';

- output port of AddSub component