Honored ContributorI want to use ep2c35f484 with 16bit ddr memory, can I implement as:
DQ[15:0] DQS[1:0] in one bank and the address, clock and control signals in another bank? the vccio of both of the banks are 2.5v, only one bank has a 1.25v ref voltage. i am a newbie, I just want someone can confirm my assumption. thanks for helping me.
Honored ContributorI remember for Cyclone III,
(1) DDR interface use x8 mode DQS group regardless of the interface width. For wider interface, like x16 in your case, you can use 2 x8 DQ groups to achieve x16 width. In this way, DQ[7:0] and DQ[15:8] might be put in different IO banks. (2) CK/CK# pins must be placed on differential I/O pins and cannot be placed on the same row or columnas the DQ pins. I don't know if Cyclone II has the same requirement. I suggest you check it in Cyclone II Device Handbook first. Or maybe you can just try to compile the DDR interface with your current pin placement. If there is anything wrong, Quartus will tell you.:)Honored ContributorThank you ,I have tried compile a DDR controller, here is my new thread.
forum/showthread.php?t=32690
