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Altera_Forum
Honored Contributor
16 years agoThere are some PLLs in the FPGAs, so you can generate higher clock rates if necessary.
You will also need to determine if the Cyclone II will be powerful enough for your application. If you have started working on the internal design, you can try and compile it for different FPGA families and see how much resources you use and if your timing requirements are met.