Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHi Dave,
There is a PCIe core serves as an Avalon-MM master. User specifies, for example, 64Mbyte BAR, or 26bit. But I found that Qsys recalculates this to lower value, based on the actual addresses of connected Avalon slaves, for example 24 bit By "worst case" I meant the most complex PCIe configuration of designs I work with. Thanks, Evgeni