Need Advice - First time PCIe device development + QSYS

Hi Evgeni,

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Just to clarify that we're talking about Endpoint, not PCIe Root device.

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Yes, the use-case I was considering was an "intelligent" PCIe peripheral device that needs to perform high-performance transactions between itself and a host (root complex). Since high-performance is required, the peripheral device needs to support being a bus master/initiator, and perform burst transactions over the PCIe bus. Typically such an interface is implemented using a DMA controller that has one address in whatever is native for the peripheral logic, eg., 32-bit Avalon-MM addresses, another address for the 64-bit PCIe bus, and a direction bit indicating whether the burst is to or from the PCIe bus.

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In this particular design PCIe is Avalon-MM master. 24-bit address is calculated automatically by Qsys system builder; it probably looks at the highest address of all connected Avalon-MM slaves.

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Sorry, this comment is not clear. "PCIe is Avalon-MM master" implies that the peripheral board is a PCIe target, where the PCIe transactions are converted by the Qsys PCIe bridge into Avalon-MM transactions. In this case the host accesses the board via the BAR registers, and the 24-bit address translation window discussed above has nothing to do with the transaction.

The 24-bit address above configures the width of the TXS Avalon-MM slave/PCIe master. Avalon-MM accesses to that 16MB range get translated into 64-bit PCIe accesses, where the LSB 24-bits are the same as the Avalon-MM address bits, but the (64-24)= 40-bits MSBs are determined by a pseudo-static register setting in the Qsys PCIe bridge control registers. The 40-bit MSBs are pseudo-static in that an SGDMA controller on the Avalon-MM bus cannot easily change the 64-bit PCIe addresses (the scatter-gather list would require 'extra' entries to write a new 40-bit address to change the PCIe MSBs).

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I didn't have a chance to deal with the case you described. The "worst case" design is 64-bit PCIe Endpoint connected to an embedded processor (PCIe Root) + DMA. So we can control memory allocation scheme on that processor.

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In what way is this a worst-case? (just so that I understand)

Cheers,

Dave