Need Advice - First time PCIe device development + QSYS

Hi Evgeni,

Just to confirm my understanding, since you've been using this core. In your address translation settings, you've got a 24-bit address (16MB ), so you can DMA from your Qsys 32-bit address space to a 16MB window in PCIe space. The MSBs of the 64-bit address are set by another register in the Qsys PCIe component.

How do you deal with the "real world" of host memory addresses that have arbitrary 64-bit addresses?

In the University Program PCIe examples I looked at, they "cheated" by having a 2GB window, and then using a memory allocation scheme on the host PC, where memory pages were restricted to lie below 2GB on the host (or at least within a fixed 2GB window).

A "real" PCIe master/initiator scatter-gather DMA controller should be able to generate an arbitrary 64-bit address for each transaction in the scatter-gather DMA list. You can create such an interface with Altera's IP cores, however, you have to use the lower-level streaming PCIe core, rather than the Qsys core.

Cheers,

Dave