Honored Contributor
Honored ContributorI wrote up my impressions of the Qsys PCIe interface in this thread:
http://www.alteraforum.com/forum/showthread.php?t=35678 The Qsys component is not very useful. A 32-bit Avalon-MM target is used to generate PCIe transactions. A 64-bit PCIe address is constructed using the 32-bit Avalon-MM address as an offset, and the 32-bit MSBs are filled in by a register setting. I feel this is a very limited solution, given that host memory pages could be located anywhere in 64-bit PCIe space. If you want a "real" PCIe initiator implementation in the FPGA, you will either need to implement your own Qsys interface, or look around and see if there is a third-party IP core that supports what you want. If you do look at third-party IP, make sure they have a decent PCIe BFM so that you can create testbenches. This is just my impression ... others can comment if they've had a better experience with Altera's PCIe offerings. Cheers, Dave
