Forum Discussion
Altera_Forum
Honored Contributor
12 years agoSorry for the double post. One more question:
For the scatter-gather DMA controller in QSYS, it appears the address bus for the m_read/m_write ports are limited to 32-bits, although in the documentation it says it is capable of 64-bit addressing in the descriptors. I would like to map the DMA controller to 2 8GB memories and the PCIe core TXS port, but I am running into an issue with the address decoding (since the decoding requires > 32 bits). What am I doing wrong? Do I need to add Avalon-MM multiplexer and select between banks ? Thank you.