My first experience with altera (MAX 10). And it didn't go well...

Hello everybody.

Finding the right FPGA can be quite a hassle. Especially when one search for a powerful one (read "lots of logic elements, DSP or memory stuff" for pure computing) with a few I/O using TQFP or similar package. In fact, nobody offers such products.

So, it's all about compromises, except for package in my case.

I first tried Lattice stuff with reasonable "little" FPGAs like the ECP2M line, the most powerful with these packages (even if there are in fact small). The 20K elements version could fit in the project I'm working for, but with no real margin. Xilinx have nothing better to offer. But Altera, with the MAX 10 series seems to be even more powerful with the TQFP 144 package (seems to me the only brand offering this kind of product).

So, let's go for the MAX10 10M50SC. Simple, fast enough, versatile, "cheap" with some interesting stuff like DSP slices and, perhaps the integrated flash memory (the main marketing argument as far I can tell) but I don't care about this feature for the moment.

How naive I was.

Two days after digging into the awful documentation, where the obscure mixes with the obvious, I couldn't even know how I can program this thing. Even the very first stage of study is stuck with the lack of relevant information. The 64 pages document "MAX 10 FPGA Configuration User Guide" is a absolute reference of absence of any real usable information. Everything is mixed up; the vocabulary is obscure and it is only a list of what the device can do. Nothing about how to do these things or even understand the overall logic.

When I read terms like "Remote System Upgrade" - perhaps my nonnative English origin mislead me - I think about a way to program the thing using for example a MCU, which is exactly what I wanted to do: sending a .sof file to the CRAM using the JTAG interface. Easy and straightforward, eh? In fact, we learn that we need a soft IP core or a "user interface" to do that. What is that? Why on earth I would need such a machinery to do what seemed to me a trivial task? So, I gave up this promising "Remote System Upgrade" which name is anything but what is seems to be.

Now, after searching, reading, reading, searching for two days, I couldn't even find anything about programming the internal RAM of the chip. Of course, using Quartus and some programming tool does the business, it would be stupid and ridiculous to need exclusively such tools to upgrade this FPGA. Even the other manufacturers like Lattice provides the JTAG instructions and format. Even the smallest micro-controller like the 8051 has the full documentation and timing of the flash memory programming using the JTAG interface (it is just an example, check out the AN105 form silicon labs. That is what I call a relevant document).

Now, I don't care about the flash memory in to FPGA. I only want to upload the CRAM image into the chip with my MPU. I have my flash memory for that with all the different firmwares. How simple and trivial could it be? For Altera, it seems irrelevant.

Even finding how the destination of the image (CRAM or Flash) is chosen is impossible: nothing is said about choosing where the image is programmed except that it is stored in files with different extensions (.sof or .pof). Isn't this an important information? It seems not, because the programming tools knows - and it is the only thing that matters. Have to go to each customer with my laptop, a USB blaster and a license of Quartus, opening the box, plugging the JTAG and upgrade the Firmware? One must be joking.

So, where is the pertinent information: the JTAG instructions for programming the device? Anyone ?

Just an example of the madness of the documentation. Take a look at page 28 of this "MAX 10 FPGA Configuration User Guide". One can see the configuration sequence. Great. Seems clear. Now take a look page 34. This makes no sense at all. On one page, there is a sequence of states to apply to the nSTATUS, CONF_DONE and nCONFIG pins. On the other hand, they are connected as fixed pull-ups. It took me some time to understand that when they write "the xxxx pin is pulled low", they forgot to add "by the FPGA itself" (if I understand correctly – except that nCONFIG is an input… Whatever). This is so badly written that I'm very afraid about the rest. Have I to fight against the documentation to even try to start something? It's not specially an Altera/Intel specificity, I've had similar experience with Microchip or Lattice, but here a new level is reached. It seems to be normal. But I'm very irritated to spend the majority of my development time with external ridiculous causes instead of working on my own stuff.

Other example that erodes the confidence about the documentation: the device pinouts. Any manufacturer offers package drawings with the pinouts. But it seems too old fashion or not "disruptive enough". Each device is described into an unreadable tableau (available on microfilms) with suspect stuff. Of course, there is no footprint or CAD data to integrate into the EDA software (except Cadence). It seems (as I could read somewhere in these forums) that it does not matter because one could create the component within minutes. Seems to me that these people never create libraries for these kind of component.

Where is the VREFB1N0 pin (you know these common mode ouput voltage pins that are NOT explained at all in the handbook) in the 10M40 and 10M50 versions? Is it normal or is there a mistake there? I had to check with Quartus to be sure that, yes, this pin is NOT available in these versions. Why ? I don't know. But, you discover this by luck, like ton of other stuff. Isn't it an important detail ? Why there is no document showing all the differences with each versions of the MAX 10 line (not only the number of logic elements) ?

These are only a few examples of crazy things I got during a few days of documentation reading, but I could add dozens of them. How one can choose so poorly documented parts? Only because it is Intel? Have I to choose a $30000 Stratix 10 to deserve good documentation? Or paying $$$ for technical support on trivial stuff?

No, really, this didn't start well.

And I still don't know how to program this thing.

Jérôme.